/*
 * Copyright     :  Copyright (C) 2021, Huawei Technologies Co. Ltd.
 * File name     :  gicd_regs_reg_offset_field.h
 * Project line  :  Platform And Key Technologies Development
 * Department    :  CAD Development Department
 * Author        :  xxx
 * Version       :  1
 * Date          :  2013/3/10
 * Description   :  The description of xxx project
 * Others        :  Generated automatically by nManager V5.1 
 * History       :  xxx 2021/10/25 08:35:55 Create file
 */

#ifndef __GICD_REGS_REG_OFFSET_FIELD_H__
#define __GICD_REGS_REG_OFFSET_FIELD_H__

#define GICD_REGS_GICD_CTLR_RWP_LEN             1
#define GICD_REGS_GICD_CTLR_RWP_OFFSET          31
#define GICD_REGS_GICD_CTLR_E1NWF_LEN           1
#define GICD_REGS_GICD_CTLR_E1NWF_OFFSET        7
#define GICD_REGS_GICD_CTLR_DS_LEN              1
#define GICD_REGS_GICD_CTLR_DS_OFFSET           6
#define GICD_REGS_GICD_CTLR_ARE_NS_LEN          1
#define GICD_REGS_GICD_CTLR_ARE_NS_OFFSET       5
#define GICD_REGS_GICD_CTLR_ARE_S_LEN           1
#define GICD_REGS_GICD_CTLR_ARE_S_OFFSET        4
#define GICD_REGS_GICD_CTLR_ENABLESGRP1_LEN     1
#define GICD_REGS_GICD_CTLR_ENABLESGRP1_OFFSET  2
#define GICD_REGS_GICD_CTLR_ENABLENSGRP1_LEN    1
#define GICD_REGS_GICD_CTLR_ENABLENSGRP1_OFFSET 1
#define GICD_REGS_GICD_CTLR_ENABLEGRP0_LEN      1
#define GICD_REGS_GICD_CTLR_ENABLEGRP0_OFFSET   0

#define GICD_REGS_GICD_CTLR_RWP_LEN             1
#define GICD_REGS_GICD_CTLR_RWP_OFFSET          31
#define GICD_REGS_GICD_CTLR_ARE_NS_LEN          1
#define GICD_REGS_GICD_CTLR_ARE_NS_OFFSET       4
#define GICD_REGS_GICD_CTLR_ENABLENSGRP1_LEN    1
#define GICD_REGS_GICD_CTLR_ENABLENSGRP1_OFFSET 1

#define GICD_REGS_GICD_TYP_NO1N_LEN             1
#define GICD_REGS_GICD_TYP_NO1N_OFFSET          25
#define GICD_REGS_GICD_TYP_A3V_LEN              1
#define GICD_REGS_GICD_TYP_A3V_OFFSET           24
#define GICD_REGS_GICD_TYP_IDBITS_LEN           5
#define GICD_REGS_GICD_TYP_IDBITS_OFFSET        19
#define GICD_REGS_GICD_TYP_DVIS_LEN             1
#define GICD_REGS_GICD_TYP_DVIS_OFFSET          18
#define GICD_REGS_GICD_TYP_LPIS_LEN             1
#define GICD_REGS_GICD_TYP_LPIS_OFFSET          17
#define GICD_REGS_GICD_TYP_MBIS_LEN             1
#define GICD_REGS_GICD_TYP_MBIS_OFFSET          16
#define GICD_REGS_GICD_TYP_LSPI_LEN             5
#define GICD_REGS_GICD_TYP_LSPI_OFFSET          11
#define GICD_REGS_GICD_TYP_SECURITYEXTN_LEN     1
#define GICD_REGS_GICD_TYP_SECURITYEXTN_OFFSET  10
#define GICD_REGS_GICD_TYP_CPUNUMBER_LEN        5
#define GICD_REGS_GICD_TYP_CPUNUMBER_OFFSET     5
#define GICD_REGS_GICD_TYP_ITLINESNUMBER_LEN    5
#define GICD_REGS_GICD_TYP_ITLINESNUMBER_OFFSET 0

#define GICD_REGS_PRODUCTID_LEN    8
#define GICD_REGS_PRODUCTID_OFFSET 24
#define GICD_REGS_VARIANT_LEN      4
#define GICD_REGS_VARIANT_OFFSET   16
#define GICD_REGS_REVISION_LEN     4
#define GICD_REGS_REVISION_OFFSET  12
#define GICD_REGS_IMPLEMENT_LEN    12
#define GICD_REGS_IMPLEMENT_OFFSET 0

#define GICD_REGS_SOKET_ID_LEN    2
#define GICD_REGS_SOKET_ID_OFFSET 2
#define GICD_REGS_DIE_ID_LEN      2
#define GICD_REGS_DIE_ID_OFFSET   0

#define GICD_REGS_GICD_SETSPI_NSR_LEN    10
#define GICD_REGS_GICD_SETSPI_NSR_OFFSET 0

#define GICD_REGS_GICD_CLRSPI_NSR_LEN    10
#define GICD_REGS_GICD_CLRSPI_NSR_OFFSET 0

#define GICD_REGS_GICD_SETSPI_SR_LEN    10
#define GICD_REGS_GICD_SETSPI_SR_OFFSET 0

#define GICD_REGS_GICD_CLRSPI_SR_LEN    10
#define GICD_REGS_GICD_CLRSPI_SR_OFFSET 0

#define GICD_REGS_GICD_PPI_IGROUP_LEN    12
#define GICD_REGS_GICD_PPI_IGROUP_OFFSET 20
#define GICD_REGS_GICD_SGI_IGROUP_LEN    16
#define GICD_REGS_GICD_SGI_IGROUP_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_0_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_0_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_1_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_1_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_2_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_2_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_3_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_3_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_4_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_4_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_5_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_5_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_6_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_6_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_7_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_7_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_8_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_8_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_9_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_9_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_10_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_10_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_11_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_11_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_12_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_12_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_13_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_13_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_14_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_14_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_15_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_15_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_16_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_16_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_17_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_17_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_18_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_18_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_19_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_19_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_20_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_20_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_21_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_21_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_22_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_22_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_23_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_23_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_24_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_24_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_25_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_25_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_26_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_26_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_27_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_27_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_28_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_28_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_29_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_29_OFFSET 0

#define GICD_REGS_GICD_SPI_IGROUP_30_LEN    32
#define GICD_REGS_GICD_SPI_IGROUP_30_OFFSET 0

#define GICD_REGS_GICD_PPI_SETENABLE_LEN    12
#define GICD_REGS_GICD_PPI_SETENABLE_OFFSET 20
#define GICD_REGS_GICD_SGI_SETENABLE_LEN    16
#define GICD_REGS_GICD_SGI_SETENABLE_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_0_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_0_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_1_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_1_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_2_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_2_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_3_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_3_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_4_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_4_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_5_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_5_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_6_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_6_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_7_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_7_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_8_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_8_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_9_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_9_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_10_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_10_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_11_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_11_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_12_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_12_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_13_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_13_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_14_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_14_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_15_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_15_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_16_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_16_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_17_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_17_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_18_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_18_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_19_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_19_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_20_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_20_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_21_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_21_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_22_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_22_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_23_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_23_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_24_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_24_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_25_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_25_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_26_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_26_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_27_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_27_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_28_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_28_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_29_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_29_OFFSET 0

#define GICD_REGS_GICD_SPI_SETENABLE_30_LEN    32
#define GICD_REGS_GICD_SPI_SETENABLE_30_OFFSET 0

#define GICD_REGS_GICD_PPI_CLRENABLE_LEN    12
#define GICD_REGS_GICD_PPI_CLRENABLE_OFFSET 20
#define GICD_REGS_GICD_SGI_CLRENABLE_LEN    16
#define GICD_REGS_GICD_SGI_CLRENABLE_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_0_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_0_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_1_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_1_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_2_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_2_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_3_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_3_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_4_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_4_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_5_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_5_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_6_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_6_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_7_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_7_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_8_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_8_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_9_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_9_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_10_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_10_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_11_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_11_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_12_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_12_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_13_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_13_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_14_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_14_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_15_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_15_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_16_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_16_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_17_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_17_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_18_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_18_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_19_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_19_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_20_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_20_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_21_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_21_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_22_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_22_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_23_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_23_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_24_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_24_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_25_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_25_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_26_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_26_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_27_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_27_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_28_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_28_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_29_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_29_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRENABLE_30_LEN    32
#define GICD_REGS_GICD_SPI_CLRENABLE_30_OFFSET 0

#define GICD_REGS_GICD_PPI_SETPEND_LEN    12
#define GICD_REGS_GICD_PPI_SETPEND_OFFSET 20
#define GICD_REGS_GICD_SGI_SETPEND_LEN    16
#define GICD_REGS_GICD_SGI_SETPEND_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_0_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_0_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_1_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_1_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_2_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_2_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_3_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_3_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_4_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_4_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_5_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_5_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_6_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_6_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_7_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_7_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_8_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_8_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_9_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_9_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_10_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_10_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_11_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_11_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_12_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_12_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_13_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_13_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_14_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_14_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_15_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_15_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_16_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_16_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_17_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_17_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_18_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_18_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_19_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_19_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_20_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_20_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_21_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_21_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_22_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_22_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_23_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_23_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_24_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_24_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_25_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_25_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_26_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_26_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_27_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_27_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_28_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_28_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_29_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_29_OFFSET 0

#define GICD_REGS_GICD_SPI_SETPEND_30_LEN    32
#define GICD_REGS_GICD_SPI_SETPEND_30_OFFSET 0

#define GICD_REGS_GICD_PPI_CLRPEND_LEN    12
#define GICD_REGS_GICD_PPI_CLRPEND_OFFSET 20
#define GICD_REGS_GICD_SGI_CLRPEND_LEN    16
#define GICD_REGS_GICD_SGI_CLRPEND_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_0_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_0_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_1_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_1_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_2_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_2_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_3_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_3_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_4_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_4_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_5_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_5_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_6_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_6_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_7_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_7_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_8_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_8_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_9_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_9_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_10_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_10_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_11_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_11_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_12_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_12_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_13_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_13_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_14_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_14_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_15_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_15_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_16_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_16_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_17_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_17_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_18_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_18_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_19_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_19_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_20_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_20_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_21_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_21_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_22_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_22_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_23_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_23_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_24_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_24_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_25_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_25_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_26_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_26_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_27_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_27_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_28_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_28_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_29_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_29_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRPEND_30_LEN    32
#define GICD_REGS_GICD_SPI_CLRPEND_30_OFFSET 0

#define GICD_REGS_GICD_PPI_SETACTIVE_LEN    12
#define GICD_REGS_GICD_PPI_SETACTIVE_OFFSET 20
#define GICD_REGS_GICD_SGI_SETACTIVE_LEN    16
#define GICD_REGS_GICD_SGI_SETACTIVE_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_0_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_0_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_1_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_1_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_2_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_2_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_3_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_3_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_4_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_4_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_5_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_5_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_6_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_6_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_7_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_7_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_8_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_8_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_9_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_9_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_10_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_10_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_11_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_11_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_12_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_12_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_13_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_13_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_14_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_14_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_15_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_15_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_16_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_16_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_17_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_17_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_18_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_18_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_19_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_19_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_20_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_20_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_21_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_21_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_22_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_22_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_23_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_23_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_24_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_24_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_25_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_25_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_26_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_26_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_27_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_27_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_28_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_28_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_29_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_29_OFFSET 0

#define GICD_REGS_GICD_SPI_SETACTIVE_30_LEN    32
#define GICD_REGS_GICD_SPI_SETACTIVE_30_OFFSET 0

#define GICD_REGS_GICD_PPI_CLRACTIVE_LEN    12
#define GICD_REGS_GICD_PPI_CLRACTIVE_OFFSET 20
#define GICD_REGS_GICD_SGI_CLRACTIVE_LEN    16
#define GICD_REGS_GICD_SGI_CLRACTIVE_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_0_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_0_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_1_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_1_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_2_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_2_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_3_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_3_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_4_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_4_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_5_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_5_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_6_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_6_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_7_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_7_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_8_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_8_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_9_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_9_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_10_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_10_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_11_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_11_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_12_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_12_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_13_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_13_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_14_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_14_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_15_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_15_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_16_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_16_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_17_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_17_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_18_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_18_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_19_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_19_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_20_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_20_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_21_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_21_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_22_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_22_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_23_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_23_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_24_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_24_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_25_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_25_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_26_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_26_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_27_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_27_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_28_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_28_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_29_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_29_OFFSET 0

#define GICD_REGS_GICD_SPI_CLRACTIVE_30_LEN    32
#define GICD_REGS_GICD_SPI_CLRACTIVE_30_OFFSET 0

#define GICD_REGS_GICD_PRIORITY_INT3_0_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_0_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_0_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_0_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_0_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_0_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_0_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_0_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_1_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_1_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_1_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_1_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_1_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_1_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_1_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_1_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_2_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_2_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_2_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_2_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_2_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_2_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_2_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_2_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_3_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_3_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_3_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_3_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_3_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_3_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_3_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_3_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_0_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_0_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_0_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_0_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_0_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_0_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_0_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_0_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_1_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_1_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_1_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_1_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_1_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_1_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_1_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_1_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_2_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_2_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_2_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_2_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_2_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_2_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_2_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_2_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_3_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_3_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_3_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_3_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_3_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_3_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_3_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_3_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_OFFSET 20
#define GICD_REGS_GICR_PRIORITY_INT1_LEN    4
#define GICD_REGS_GICR_PRIORITY_INT1_OFFSET 12
#define GICD_REGS_GICR_PRIORITY_INT0_LEN    4
#define GICD_REGS_GICR_PRIORITY_INT0_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_OFFSET 19
#define GICD_REGS_GICR_PRIORITY_INT1_LEN    5
#define GICD_REGS_GICR_PRIORITY_INT1_OFFSET 11
#define GICD_REGS_GICR_PRIORITY_INT0_LEN    5
#define GICD_REGS_GICR_PRIORITY_INT0_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_0_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_0_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_0_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_0_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_0_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_0_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_0_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_0_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_1_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_1_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_1_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_1_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_1_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_1_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_1_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_1_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_0_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_0_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_0_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_0_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_0_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_0_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_0_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_0_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_1_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_1_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_1_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_1_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_1_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_1_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_1_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_1_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_0_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_0_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_0_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_0_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_0_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_0_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_0_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_0_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_1_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_1_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_1_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_1_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_1_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_1_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_1_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_1_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_2_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_2_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_2_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_2_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_2_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_2_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_2_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_2_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_3_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_3_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_3_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_3_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_3_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_3_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_3_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_3_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_4_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_4_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_4_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_4_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_4_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_4_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_4_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_4_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_5_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_5_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_5_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_5_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_5_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_5_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_5_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_5_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_6_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_6_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_6_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_6_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_6_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_6_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_6_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_6_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_7_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_7_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_7_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_7_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_7_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_7_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_7_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_7_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_8_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_8_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_8_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_8_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_8_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_8_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_8_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_8_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_9_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_9_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_9_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_9_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_9_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_9_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_9_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_9_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_10_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_10_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_10_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_10_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_10_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_10_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_10_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_10_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_11_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_11_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_11_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_11_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_11_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_11_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_11_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_11_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_12_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_12_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_12_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_12_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_12_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_12_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_12_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_12_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_13_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_13_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_13_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_13_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_13_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_13_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_13_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_13_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_14_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_14_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_14_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_14_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_14_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_14_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_14_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_14_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_15_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_15_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_15_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_15_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_15_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_15_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_15_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_15_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_16_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_16_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_16_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_16_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_16_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_16_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_16_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_16_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_17_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_17_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_17_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_17_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_17_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_17_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_17_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_17_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_18_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_18_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_18_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_18_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_18_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_18_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_18_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_18_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_19_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_19_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_19_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_19_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_19_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_19_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_19_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_19_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_20_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_20_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_20_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_20_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_20_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_20_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_20_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_20_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_21_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_21_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_21_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_21_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_21_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_21_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_21_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_21_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_22_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_22_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_22_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_22_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_22_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_22_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_22_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_22_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_23_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_23_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_23_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_23_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_23_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_23_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_23_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_23_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_24_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_24_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_24_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_24_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_24_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_24_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_24_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_24_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_25_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_25_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_25_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_25_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_25_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_25_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_25_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_25_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_26_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_26_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_26_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_26_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_26_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_26_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_26_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_26_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_27_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_27_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_27_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_27_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_27_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_27_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_27_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_27_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_28_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_28_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_28_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_28_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_28_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_28_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_28_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_28_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_29_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_29_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_29_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_29_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_29_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_29_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_29_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_29_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_30_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_30_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_30_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_30_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_30_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_30_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_30_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_30_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_31_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_31_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_31_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_31_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_31_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_31_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_31_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_31_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_32_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_32_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_32_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_32_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_32_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_32_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_32_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_32_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_33_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_33_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_33_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_33_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_33_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_33_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_33_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_33_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_34_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_34_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_34_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_34_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_34_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_34_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_34_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_34_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_35_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_35_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_35_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_35_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_35_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_35_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_35_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_35_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_36_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_36_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_36_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_36_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_36_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_36_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_36_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_36_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_37_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_37_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_37_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_37_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_37_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_37_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_37_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_37_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_38_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_38_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_38_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_38_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_38_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_38_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_38_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_38_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_39_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_39_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_39_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_39_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_39_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_39_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_39_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_39_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_40_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_40_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_40_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_40_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_40_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_40_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_40_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_40_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_41_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_41_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_41_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_41_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_41_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_41_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_41_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_41_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_42_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_42_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_42_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_42_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_42_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_42_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_42_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_42_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_43_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_43_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_43_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_43_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_43_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_43_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_43_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_43_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_44_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_44_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_44_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_44_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_44_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_44_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_44_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_44_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_45_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_45_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_45_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_45_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_45_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_45_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_45_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_45_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_46_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_46_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_46_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_46_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_46_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_46_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_46_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_46_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_47_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_47_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_47_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_47_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_47_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_47_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_47_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_47_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_48_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_48_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_48_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_48_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_48_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_48_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_48_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_48_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_49_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_49_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_49_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_49_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_49_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_49_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_49_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_49_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_50_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_50_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_50_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_50_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_50_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_50_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_50_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_50_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_51_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_51_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_51_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_51_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_51_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_51_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_51_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_51_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_52_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_52_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_52_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_52_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_52_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_52_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_52_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_52_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_53_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_53_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_53_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_53_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_53_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_53_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_53_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_53_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_54_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_54_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_54_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_54_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_54_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_54_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_54_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_54_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_55_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_55_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_55_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_55_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_55_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_55_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_55_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_55_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_56_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_56_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_56_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_56_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_56_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_56_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_56_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_56_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_57_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_57_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_57_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_57_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_57_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_57_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_57_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_57_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_58_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_58_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_58_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_58_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_58_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_58_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_58_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_58_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_59_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_59_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_59_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_59_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_59_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_59_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_59_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_59_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_60_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_60_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_60_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_60_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_60_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_60_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_60_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_60_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_61_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_61_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_61_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_61_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_61_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_61_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_61_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_61_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_62_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_62_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_62_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_62_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_62_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_62_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_62_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_62_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_63_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_63_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_63_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_63_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_63_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_63_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_63_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_63_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_64_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_64_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_64_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_64_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_64_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_64_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_64_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_64_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_65_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_65_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_65_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_65_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_65_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_65_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_65_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_65_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_66_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_66_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_66_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_66_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_66_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_66_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_66_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_66_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_67_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_67_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_67_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_67_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_67_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_67_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_67_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_67_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_68_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_68_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_68_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_68_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_68_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_68_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_68_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_68_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_69_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_69_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_69_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_69_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_69_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_69_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_69_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_69_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_70_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_70_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_70_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_70_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_70_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_70_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_70_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_70_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_71_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_71_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_71_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_71_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_71_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_71_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_71_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_71_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_72_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_72_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_72_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_72_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_72_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_72_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_72_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_72_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_73_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_73_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_73_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_73_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_73_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_73_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_73_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_73_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_74_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_74_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_74_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_74_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_74_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_74_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_74_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_74_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_75_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_75_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_75_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_75_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_75_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_75_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_75_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_75_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_76_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_76_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_76_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_76_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_76_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_76_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_76_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_76_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_77_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_77_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_77_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_77_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_77_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_77_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_77_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_77_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_78_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_78_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_78_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_78_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_78_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_78_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_78_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_78_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_79_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_79_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_79_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_79_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_79_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_79_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_79_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_79_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_80_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_80_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_80_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_80_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_80_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_80_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_80_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_80_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_81_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_81_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_81_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_81_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_81_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_81_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_81_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_81_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_82_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_82_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_82_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_82_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_82_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_82_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_82_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_82_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_83_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_83_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_83_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_83_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_83_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_83_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_83_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_83_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_84_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_84_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_84_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_84_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_84_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_84_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_84_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_84_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_85_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_85_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_85_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_85_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_85_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_85_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_85_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_85_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_86_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_86_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_86_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_86_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_86_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_86_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_86_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_86_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_87_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_87_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_87_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_87_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_87_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_87_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_87_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_87_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_88_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_88_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_88_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_88_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_88_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_88_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_88_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_88_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_89_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_89_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_89_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_89_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_89_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_89_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_89_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_89_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_90_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_90_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_90_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_90_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_90_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_90_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_90_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_90_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_91_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_91_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_91_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_91_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_91_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_91_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_91_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_91_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_92_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_92_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_92_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_92_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_92_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_92_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_92_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_92_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_93_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_93_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_93_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_93_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_93_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_93_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_93_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_93_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_94_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_94_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_94_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_94_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_94_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_94_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_94_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_94_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_95_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_95_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_95_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_95_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_95_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_95_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_95_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_95_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_96_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_96_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_96_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_96_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_96_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_96_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_96_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_96_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_97_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_97_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_97_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_97_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_97_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_97_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_97_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_97_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_98_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_98_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_98_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_98_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_98_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_98_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_98_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_98_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_99_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_99_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_99_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_99_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_99_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_99_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_99_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_99_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_100_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_100_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_100_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_100_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_100_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_100_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_100_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_100_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_101_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_101_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_101_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_101_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_101_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_101_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_101_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_101_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_102_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_102_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_102_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_102_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_102_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_102_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_102_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_102_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_103_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_103_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_103_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_103_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_103_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_103_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_103_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_103_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_104_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_104_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_104_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_104_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_104_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_104_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_104_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_104_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_105_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_105_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_105_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_105_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_105_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_105_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_105_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_105_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_106_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_106_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_106_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_106_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_106_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_106_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_106_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_106_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_107_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_107_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_107_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_107_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_107_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_107_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_107_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_107_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_108_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_108_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_108_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_108_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_108_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_108_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_108_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_108_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_109_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_109_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_109_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_109_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_109_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_109_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_109_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_109_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_110_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_110_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_110_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_110_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_110_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_110_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_110_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_110_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_111_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_111_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_111_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_111_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_111_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_111_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_111_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_111_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_112_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_112_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_112_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_112_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_112_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_112_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_112_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_112_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_113_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_113_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_113_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_113_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_113_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_113_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_113_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_113_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_114_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_114_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_114_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_114_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_114_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_114_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_114_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_114_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_115_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_115_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_115_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_115_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_115_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_115_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_115_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_115_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_116_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_116_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_116_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_116_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_116_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_116_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_116_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_116_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_117_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_117_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_117_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_117_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_117_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_117_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_117_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_117_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_118_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_118_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_118_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_118_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_118_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_118_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_118_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_118_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_119_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_119_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_119_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_119_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_119_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_119_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_119_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_119_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_120_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_120_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_120_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_120_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_120_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_120_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_120_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_120_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_121_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_121_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_121_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_121_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_121_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_121_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_121_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_121_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_122_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_122_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_122_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_122_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_122_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_122_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_122_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_122_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_123_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_123_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_123_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_123_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_123_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_123_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_123_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_123_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_124_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_124_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_124_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_124_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_124_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_124_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_124_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_124_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_125_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_125_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_125_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_125_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_125_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_125_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_125_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_125_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_126_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_126_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_126_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_126_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_126_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_126_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_126_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_126_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_127_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_127_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_127_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_127_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_127_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_127_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_127_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_127_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_128_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_128_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_128_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_128_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_128_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_128_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_128_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_128_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_129_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_129_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_129_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_129_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_129_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_129_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_129_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_129_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_130_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_130_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_130_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_130_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_130_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_130_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_130_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_130_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_131_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_131_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_131_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_131_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_131_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_131_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_131_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_131_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_132_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_132_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_132_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_132_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_132_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_132_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_132_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_132_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_133_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_133_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_133_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_133_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_133_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_133_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_133_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_133_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_134_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_134_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_134_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_134_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_134_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_134_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_134_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_134_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_135_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_135_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_135_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_135_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_135_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_135_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_135_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_135_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_136_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_136_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_136_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_136_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_136_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_136_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_136_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_136_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_137_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_137_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_137_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_137_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_137_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_137_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_137_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_137_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_138_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_138_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_138_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_138_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_138_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_138_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_138_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_138_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_139_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_139_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_139_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_139_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_139_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_139_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_139_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_139_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_140_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_140_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_140_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_140_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_140_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_140_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_140_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_140_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_141_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_141_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_141_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_141_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_141_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_141_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_141_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_141_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_142_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_142_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_142_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_142_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_142_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_142_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_142_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_142_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_143_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_143_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_143_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_143_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_143_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_143_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_143_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_143_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_144_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_144_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_144_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_144_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_144_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_144_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_144_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_144_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_145_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_145_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_145_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_145_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_145_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_145_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_145_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_145_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_146_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_146_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_146_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_146_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_146_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_146_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_146_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_146_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_147_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_147_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_147_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_147_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_147_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_147_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_147_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_147_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_148_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_148_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_148_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_148_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_148_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_148_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_148_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_148_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_149_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_149_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_149_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_149_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_149_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_149_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_149_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_149_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_150_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_150_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_150_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_150_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_150_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_150_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_150_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_150_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_151_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_151_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_151_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_151_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_151_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_151_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_151_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_151_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_152_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_152_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_152_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_152_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_152_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_152_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_152_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_152_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_153_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_153_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_153_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_153_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_153_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_153_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_153_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_153_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_154_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_154_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_154_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_154_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_154_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_154_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_154_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_154_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_155_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_155_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_155_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_155_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_155_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_155_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_155_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_155_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_156_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_156_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_156_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_156_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_156_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_156_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_156_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_156_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_157_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_157_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_157_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_157_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_157_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_157_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_157_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_157_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_158_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_158_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_158_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_158_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_158_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_158_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_158_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_158_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_159_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_159_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_159_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_159_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_159_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_159_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_159_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_159_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_160_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_160_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_160_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_160_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_160_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_160_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_160_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_160_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_161_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_161_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_161_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_161_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_161_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_161_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_161_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_161_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_162_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_162_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_162_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_162_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_162_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_162_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_162_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_162_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_163_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_163_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_163_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_163_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_163_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_163_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_163_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_163_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_164_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_164_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_164_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_164_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_164_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_164_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_164_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_164_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_165_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_165_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_165_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_165_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_165_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_165_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_165_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_165_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_166_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_166_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_166_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_166_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_166_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_166_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_166_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_166_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_167_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_167_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_167_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_167_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_167_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_167_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_167_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_167_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_168_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_168_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_168_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_168_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_168_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_168_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_168_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_168_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_169_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_169_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_169_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_169_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_169_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_169_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_169_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_169_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_170_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_170_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_170_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_170_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_170_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_170_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_170_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_170_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_171_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_171_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_171_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_171_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_171_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_171_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_171_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_171_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_172_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_172_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_172_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_172_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_172_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_172_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_172_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_172_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_173_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_173_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_173_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_173_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_173_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_173_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_173_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_173_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_174_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_174_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_174_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_174_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_174_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_174_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_174_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_174_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_175_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_175_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_175_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_175_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_175_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_175_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_175_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_175_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_176_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_176_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_176_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_176_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_176_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_176_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_176_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_176_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_177_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_177_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_177_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_177_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_177_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_177_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_177_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_177_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_178_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_178_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_178_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_178_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_178_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_178_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_178_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_178_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_179_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_179_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_179_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_179_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_179_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_179_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_179_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_179_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_180_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_180_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_180_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_180_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_180_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_180_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_180_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_180_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_181_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_181_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_181_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_181_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_181_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_181_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_181_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_181_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_182_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_182_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_182_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_182_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_182_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_182_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_182_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_182_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_183_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_183_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_183_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_183_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_183_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_183_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_183_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_183_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_184_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_184_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_184_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_184_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_184_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_184_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_184_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_184_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_185_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_185_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_185_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_185_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_185_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_185_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_185_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_185_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_186_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_186_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_186_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_186_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_186_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_186_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_186_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_186_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_187_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_187_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_187_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_187_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_187_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_187_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_187_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_187_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_188_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_188_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_188_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_188_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_188_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_188_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_188_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_188_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_189_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_189_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_189_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_189_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_189_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_189_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_189_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_189_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_190_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_190_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_190_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_190_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_190_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_190_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_190_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_190_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_191_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_191_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_191_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_191_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_191_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_191_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_191_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_191_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_192_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_192_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_192_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_192_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_192_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_192_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_192_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_192_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_193_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_193_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_193_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_193_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_193_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_193_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_193_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_193_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_194_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_194_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_194_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_194_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_194_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_194_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_194_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_194_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_195_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_195_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_195_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_195_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_195_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_195_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_195_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_195_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_196_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_196_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_196_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_196_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_196_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_196_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_196_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_196_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_197_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_197_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_197_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_197_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_197_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_197_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_197_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_197_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_198_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_198_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_198_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_198_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_198_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_198_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_198_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_198_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_199_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_199_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_199_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_199_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_199_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_199_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_199_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_199_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_200_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_200_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_200_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_200_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_200_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_200_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_200_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_200_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_201_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_201_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_201_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_201_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_201_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_201_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_201_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_201_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_202_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_202_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_202_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_202_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_202_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_202_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_202_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_202_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_203_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_203_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_203_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_203_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_203_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_203_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_203_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_203_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_204_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_204_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_204_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_204_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_204_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_204_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_204_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_204_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_205_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_205_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_205_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_205_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_205_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_205_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_205_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_205_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_206_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_206_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_206_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_206_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_206_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_206_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_206_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_206_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_207_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_207_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_207_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_207_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_207_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_207_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_207_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_207_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_208_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_208_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_208_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_208_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_208_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_208_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_208_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_208_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_209_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_209_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_209_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_209_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_209_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_209_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_209_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_209_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_210_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_210_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_210_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_210_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_210_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_210_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_210_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_210_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_211_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_211_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_211_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_211_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_211_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_211_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_211_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_211_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_212_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_212_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_212_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_212_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_212_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_212_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_212_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_212_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_213_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_213_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_213_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_213_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_213_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_213_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_213_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_213_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_214_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_214_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_214_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_214_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_214_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_214_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_214_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_214_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_215_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_215_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_215_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_215_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_215_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_215_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_215_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_215_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_216_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_216_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_216_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_216_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_216_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_216_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_216_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_216_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_217_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_217_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_217_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_217_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_217_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_217_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_217_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_217_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_218_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_218_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_218_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_218_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_218_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_218_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_218_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_218_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_219_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_219_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_219_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_219_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_219_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_219_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_219_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_219_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_220_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_220_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_220_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_220_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_220_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_220_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_220_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_220_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_221_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_221_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_221_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_221_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_221_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_221_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_221_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_221_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_222_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_222_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_222_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_222_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_222_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_222_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_222_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_222_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_223_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_223_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_223_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_223_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_223_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_223_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_223_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_223_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_224_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_224_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_224_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_224_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_224_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_224_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_224_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_224_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_225_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_225_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_225_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_225_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_225_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_225_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_225_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_225_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_226_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_226_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_226_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_226_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_226_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_226_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_226_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_226_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_227_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_227_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_227_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_227_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_227_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_227_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_227_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_227_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_228_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_228_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_228_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_228_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_228_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_228_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_228_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_228_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_229_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_229_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_229_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_229_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_229_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_229_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_229_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_229_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_230_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_230_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_230_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_230_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_230_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_230_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_230_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_230_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_231_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_231_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_231_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_231_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_231_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_231_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_231_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_231_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_232_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_232_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_232_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_232_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_232_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_232_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_232_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_232_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_233_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_233_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_233_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_233_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_233_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_233_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_233_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_233_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_234_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_234_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_234_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_234_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_234_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_234_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_234_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_234_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_235_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_235_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_235_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_235_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_235_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_235_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_235_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_235_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_236_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_236_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_236_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_236_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_236_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_236_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_236_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_236_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_237_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_237_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_237_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_237_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_237_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_237_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_237_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_237_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_238_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_238_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_238_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_238_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_238_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_238_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_238_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_238_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_239_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_239_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_239_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_239_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_239_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_239_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_239_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_239_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_240_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_240_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_240_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_240_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_240_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_240_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_240_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_240_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_241_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_241_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_241_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_241_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_241_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_241_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_241_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_241_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_242_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_242_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_242_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_242_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_242_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_242_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_242_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_242_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_243_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_243_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_243_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_243_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_243_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_243_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_243_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_243_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_244_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_244_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_244_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_244_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_244_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_244_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_244_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_244_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_245_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_245_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_245_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_245_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_245_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_245_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_245_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_245_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_246_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_246_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_246_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_246_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_246_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_246_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_246_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_246_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_247_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT3_247_OFFSET 28
#define GICD_REGS_GICD_PRIORITY_INT2_247_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT2_247_OFFSET 20
#define GICD_REGS_GICD_PRIORITY_INT1_247_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT1_247_OFFSET 12
#define GICD_REGS_GICD_PRIORITY_INT0_247_LEN    4
#define GICD_REGS_GICD_PRIORITY_INT0_247_OFFSET 4

#define GICD_REGS_GICD_PRIORITY_INT3_0_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_0_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_0_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_0_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_0_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_0_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_0_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_0_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_1_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_1_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_1_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_1_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_1_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_1_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_1_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_1_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_2_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_2_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_2_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_2_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_2_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_2_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_2_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_2_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_3_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_3_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_3_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_3_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_3_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_3_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_3_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_3_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_4_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_4_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_4_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_4_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_4_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_4_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_4_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_4_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_5_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_5_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_5_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_5_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_5_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_5_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_5_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_5_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_6_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_6_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_6_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_6_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_6_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_6_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_6_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_6_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_7_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_7_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_7_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_7_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_7_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_7_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_7_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_7_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_8_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_8_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_8_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_8_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_8_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_8_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_8_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_8_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_9_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_9_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_9_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_9_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_9_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_9_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_9_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_9_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_10_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_10_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_10_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_10_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_10_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_10_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_10_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_10_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_11_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_11_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_11_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_11_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_11_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_11_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_11_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_11_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_12_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_12_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_12_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_12_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_12_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_12_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_12_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_12_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_13_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_13_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_13_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_13_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_13_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_13_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_13_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_13_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_14_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_14_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_14_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_14_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_14_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_14_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_14_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_14_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_15_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_15_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_15_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_15_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_15_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_15_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_15_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_15_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_16_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_16_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_16_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_16_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_16_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_16_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_16_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_16_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_17_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_17_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_17_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_17_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_17_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_17_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_17_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_17_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_18_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_18_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_18_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_18_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_18_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_18_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_18_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_18_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_19_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_19_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_19_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_19_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_19_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_19_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_19_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_19_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_20_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_20_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_20_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_20_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_20_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_20_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_20_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_20_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_21_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_21_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_21_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_21_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_21_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_21_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_21_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_21_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_22_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_22_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_22_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_22_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_22_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_22_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_22_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_22_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_23_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_23_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_23_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_23_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_23_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_23_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_23_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_23_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_24_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_24_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_24_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_24_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_24_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_24_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_24_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_24_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_25_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_25_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_25_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_25_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_25_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_25_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_25_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_25_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_26_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_26_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_26_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_26_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_26_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_26_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_26_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_26_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_27_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_27_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_27_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_27_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_27_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_27_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_27_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_27_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_28_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_28_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_28_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_28_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_28_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_28_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_28_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_28_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_29_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_29_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_29_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_29_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_29_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_29_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_29_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_29_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_30_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_30_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_30_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_30_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_30_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_30_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_30_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_30_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_31_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_31_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_31_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_31_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_31_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_31_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_31_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_31_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_32_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_32_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_32_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_32_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_32_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_32_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_32_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_32_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_33_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_33_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_33_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_33_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_33_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_33_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_33_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_33_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_34_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_34_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_34_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_34_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_34_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_34_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_34_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_34_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_35_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_35_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_35_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_35_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_35_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_35_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_35_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_35_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_36_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_36_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_36_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_36_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_36_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_36_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_36_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_36_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_37_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_37_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_37_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_37_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_37_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_37_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_37_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_37_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_38_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_38_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_38_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_38_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_38_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_38_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_38_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_38_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_39_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_39_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_39_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_39_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_39_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_39_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_39_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_39_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_40_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_40_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_40_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_40_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_40_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_40_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_40_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_40_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_41_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_41_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_41_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_41_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_41_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_41_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_41_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_41_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_42_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_42_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_42_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_42_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_42_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_42_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_42_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_42_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_43_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_43_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_43_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_43_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_43_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_43_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_43_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_43_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_44_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_44_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_44_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_44_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_44_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_44_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_44_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_44_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_45_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_45_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_45_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_45_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_45_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_45_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_45_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_45_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_46_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_46_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_46_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_46_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_46_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_46_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_46_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_46_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_47_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_47_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_47_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_47_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_47_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_47_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_47_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_47_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_48_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_48_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_48_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_48_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_48_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_48_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_48_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_48_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_49_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_49_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_49_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_49_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_49_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_49_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_49_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_49_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_50_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_50_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_50_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_50_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_50_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_50_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_50_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_50_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_51_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_51_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_51_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_51_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_51_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_51_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_51_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_51_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_52_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_52_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_52_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_52_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_52_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_52_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_52_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_52_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_53_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_53_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_53_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_53_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_53_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_53_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_53_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_53_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_54_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_54_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_54_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_54_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_54_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_54_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_54_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_54_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_55_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_55_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_55_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_55_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_55_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_55_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_55_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_55_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_56_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_56_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_56_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_56_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_56_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_56_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_56_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_56_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_57_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_57_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_57_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_57_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_57_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_57_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_57_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_57_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_58_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_58_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_58_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_58_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_58_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_58_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_58_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_58_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_59_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_59_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_59_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_59_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_59_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_59_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_59_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_59_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_60_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_60_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_60_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_60_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_60_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_60_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_60_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_60_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_61_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_61_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_61_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_61_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_61_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_61_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_61_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_61_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_62_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_62_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_62_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_62_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_62_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_62_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_62_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_62_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_63_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_63_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_63_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_63_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_63_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_63_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_63_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_63_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_64_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_64_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_64_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_64_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_64_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_64_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_64_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_64_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_65_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_65_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_65_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_65_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_65_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_65_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_65_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_65_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_66_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_66_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_66_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_66_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_66_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_66_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_66_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_66_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_67_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_67_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_67_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_67_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_67_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_67_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_67_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_67_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_68_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_68_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_68_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_68_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_68_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_68_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_68_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_68_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_69_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_69_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_69_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_69_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_69_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_69_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_69_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_69_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_70_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_70_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_70_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_70_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_70_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_70_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_70_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_70_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_71_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_71_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_71_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_71_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_71_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_71_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_71_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_71_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_72_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_72_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_72_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_72_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_72_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_72_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_72_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_72_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_73_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_73_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_73_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_73_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_73_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_73_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_73_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_73_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_74_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_74_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_74_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_74_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_74_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_74_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_74_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_74_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_75_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_75_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_75_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_75_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_75_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_75_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_75_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_75_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_76_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_76_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_76_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_76_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_76_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_76_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_76_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_76_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_77_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_77_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_77_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_77_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_77_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_77_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_77_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_77_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_78_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_78_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_78_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_78_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_78_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_78_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_78_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_78_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_79_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_79_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_79_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_79_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_79_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_79_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_79_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_79_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_80_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_80_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_80_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_80_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_80_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_80_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_80_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_80_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_81_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_81_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_81_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_81_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_81_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_81_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_81_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_81_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_82_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_82_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_82_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_82_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_82_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_82_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_82_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_82_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_83_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_83_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_83_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_83_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_83_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_83_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_83_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_83_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_84_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_84_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_84_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_84_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_84_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_84_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_84_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_84_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_85_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_85_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_85_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_85_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_85_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_85_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_85_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_85_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_86_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_86_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_86_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_86_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_86_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_86_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_86_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_86_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_87_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_87_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_87_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_87_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_87_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_87_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_87_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_87_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_88_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_88_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_88_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_88_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_88_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_88_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_88_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_88_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_89_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_89_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_89_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_89_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_89_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_89_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_89_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_89_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_90_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_90_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_90_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_90_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_90_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_90_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_90_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_90_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_91_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_91_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_91_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_91_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_91_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_91_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_91_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_91_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_92_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_92_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_92_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_92_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_92_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_92_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_92_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_92_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_93_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_93_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_93_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_93_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_93_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_93_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_93_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_93_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_94_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_94_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_94_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_94_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_94_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_94_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_94_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_94_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_95_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_95_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_95_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_95_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_95_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_95_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_95_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_95_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_96_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_96_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_96_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_96_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_96_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_96_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_96_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_96_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_97_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_97_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_97_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_97_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_97_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_97_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_97_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_97_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_98_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_98_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_98_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_98_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_98_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_98_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_98_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_98_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_99_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_99_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_99_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_99_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_99_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_99_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_99_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_99_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_100_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_100_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_100_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_100_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_100_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_100_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_100_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_100_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_101_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_101_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_101_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_101_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_101_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_101_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_101_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_101_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_102_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_102_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_102_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_102_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_102_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_102_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_102_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_102_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_103_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_103_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_103_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_103_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_103_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_103_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_103_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_103_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_104_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_104_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_104_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_104_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_104_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_104_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_104_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_104_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_105_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_105_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_105_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_105_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_105_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_105_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_105_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_105_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_106_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_106_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_106_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_106_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_106_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_106_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_106_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_106_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_107_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_107_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_107_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_107_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_107_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_107_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_107_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_107_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_108_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_108_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_108_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_108_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_108_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_108_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_108_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_108_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_109_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_109_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_109_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_109_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_109_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_109_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_109_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_109_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_110_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_110_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_110_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_110_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_110_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_110_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_110_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_110_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_111_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_111_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_111_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_111_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_111_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_111_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_111_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_111_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_112_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_112_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_112_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_112_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_112_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_112_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_112_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_112_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_113_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_113_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_113_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_113_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_113_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_113_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_113_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_113_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_114_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_114_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_114_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_114_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_114_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_114_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_114_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_114_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_115_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_115_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_115_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_115_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_115_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_115_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_115_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_115_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_116_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_116_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_116_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_116_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_116_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_116_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_116_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_116_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_117_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_117_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_117_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_117_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_117_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_117_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_117_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_117_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_118_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_118_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_118_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_118_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_118_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_118_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_118_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_118_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_119_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_119_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_119_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_119_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_119_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_119_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_119_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_119_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_120_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_120_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_120_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_120_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_120_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_120_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_120_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_120_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_121_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_121_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_121_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_121_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_121_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_121_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_121_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_121_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_122_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_122_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_122_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_122_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_122_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_122_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_122_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_122_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_123_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_123_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_123_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_123_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_123_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_123_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_123_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_123_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_124_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_124_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_124_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_124_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_124_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_124_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_124_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_124_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_125_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_125_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_125_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_125_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_125_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_125_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_125_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_125_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_126_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_126_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_126_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_126_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_126_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_126_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_126_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_126_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_127_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_127_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_127_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_127_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_127_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_127_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_127_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_127_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_128_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_128_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_128_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_128_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_128_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_128_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_128_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_128_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_129_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_129_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_129_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_129_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_129_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_129_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_129_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_129_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_130_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_130_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_130_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_130_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_130_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_130_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_130_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_130_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_131_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_131_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_131_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_131_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_131_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_131_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_131_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_131_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_132_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_132_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_132_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_132_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_132_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_132_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_132_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_132_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_133_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_133_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_133_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_133_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_133_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_133_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_133_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_133_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_134_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_134_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_134_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_134_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_134_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_134_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_134_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_134_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_135_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_135_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_135_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_135_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_135_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_135_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_135_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_135_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_136_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_136_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_136_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_136_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_136_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_136_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_136_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_136_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_137_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_137_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_137_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_137_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_137_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_137_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_137_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_137_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_138_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_138_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_138_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_138_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_138_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_138_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_138_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_138_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_139_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_139_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_139_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_139_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_139_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_139_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_139_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_139_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_140_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_140_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_140_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_140_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_140_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_140_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_140_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_140_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_141_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_141_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_141_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_141_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_141_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_141_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_141_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_141_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_142_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_142_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_142_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_142_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_142_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_142_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_142_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_142_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_143_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_143_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_143_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_143_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_143_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_143_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_143_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_143_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_144_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_144_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_144_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_144_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_144_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_144_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_144_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_144_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_145_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_145_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_145_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_145_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_145_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_145_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_145_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_145_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_146_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_146_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_146_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_146_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_146_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_146_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_146_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_146_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_147_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_147_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_147_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_147_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_147_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_147_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_147_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_147_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_148_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_148_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_148_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_148_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_148_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_148_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_148_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_148_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_149_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_149_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_149_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_149_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_149_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_149_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_149_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_149_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_150_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_150_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_150_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_150_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_150_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_150_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_150_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_150_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_151_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_151_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_151_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_151_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_151_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_151_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_151_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_151_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_152_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_152_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_152_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_152_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_152_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_152_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_152_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_152_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_153_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_153_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_153_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_153_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_153_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_153_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_153_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_153_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_154_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_154_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_154_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_154_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_154_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_154_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_154_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_154_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_155_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_155_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_155_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_155_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_155_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_155_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_155_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_155_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_156_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_156_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_156_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_156_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_156_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_156_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_156_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_156_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_157_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_157_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_157_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_157_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_157_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_157_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_157_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_157_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_158_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_158_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_158_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_158_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_158_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_158_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_158_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_158_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_159_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_159_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_159_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_159_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_159_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_159_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_159_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_159_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_160_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_160_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_160_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_160_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_160_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_160_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_160_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_160_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_161_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_161_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_161_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_161_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_161_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_161_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_161_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_161_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_162_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_162_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_162_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_162_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_162_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_162_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_162_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_162_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_163_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_163_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_163_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_163_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_163_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_163_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_163_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_163_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_164_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_164_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_164_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_164_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_164_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_164_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_164_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_164_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_165_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_165_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_165_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_165_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_165_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_165_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_165_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_165_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_166_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_166_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_166_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_166_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_166_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_166_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_166_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_166_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_167_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_167_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_167_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_167_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_167_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_167_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_167_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_167_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_168_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_168_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_168_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_168_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_168_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_168_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_168_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_168_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_169_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_169_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_169_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_169_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_169_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_169_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_169_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_169_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_170_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_170_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_170_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_170_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_170_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_170_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_170_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_170_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_171_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_171_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_171_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_171_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_171_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_171_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_171_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_171_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_172_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_172_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_172_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_172_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_172_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_172_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_172_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_172_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_173_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_173_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_173_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_173_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_173_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_173_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_173_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_173_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_174_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_174_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_174_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_174_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_174_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_174_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_174_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_174_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_175_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_175_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_175_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_175_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_175_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_175_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_175_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_175_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_176_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_176_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_176_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_176_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_176_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_176_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_176_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_176_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_177_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_177_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_177_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_177_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_177_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_177_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_177_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_177_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_178_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_178_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_178_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_178_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_178_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_178_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_178_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_178_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_179_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_179_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_179_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_179_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_179_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_179_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_179_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_179_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_180_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_180_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_180_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_180_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_180_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_180_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_180_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_180_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_181_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_181_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_181_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_181_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_181_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_181_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_181_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_181_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_182_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_182_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_182_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_182_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_182_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_182_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_182_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_182_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_183_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_183_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_183_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_183_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_183_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_183_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_183_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_183_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_184_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_184_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_184_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_184_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_184_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_184_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_184_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_184_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_185_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_185_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_185_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_185_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_185_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_185_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_185_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_185_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_186_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_186_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_186_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_186_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_186_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_186_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_186_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_186_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_187_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_187_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_187_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_187_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_187_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_187_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_187_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_187_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_188_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_188_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_188_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_188_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_188_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_188_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_188_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_188_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_189_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_189_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_189_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_189_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_189_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_189_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_189_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_189_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_190_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_190_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_190_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_190_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_190_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_190_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_190_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_190_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_191_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_191_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_191_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_191_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_191_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_191_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_191_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_191_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_192_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_192_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_192_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_192_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_192_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_192_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_192_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_192_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_193_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_193_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_193_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_193_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_193_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_193_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_193_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_193_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_194_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_194_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_194_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_194_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_194_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_194_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_194_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_194_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_195_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_195_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_195_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_195_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_195_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_195_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_195_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_195_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_196_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_196_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_196_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_196_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_196_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_196_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_196_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_196_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_197_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_197_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_197_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_197_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_197_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_197_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_197_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_197_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_198_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_198_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_198_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_198_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_198_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_198_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_198_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_198_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_199_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_199_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_199_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_199_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_199_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_199_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_199_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_199_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_200_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_200_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_200_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_200_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_200_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_200_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_200_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_200_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_201_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_201_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_201_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_201_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_201_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_201_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_201_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_201_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_202_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_202_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_202_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_202_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_202_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_202_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_202_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_202_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_203_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_203_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_203_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_203_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_203_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_203_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_203_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_203_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_204_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_204_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_204_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_204_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_204_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_204_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_204_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_204_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_205_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_205_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_205_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_205_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_205_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_205_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_205_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_205_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_206_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_206_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_206_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_206_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_206_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_206_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_206_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_206_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_207_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_207_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_207_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_207_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_207_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_207_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_207_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_207_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_208_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_208_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_208_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_208_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_208_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_208_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_208_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_208_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_209_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_209_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_209_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_209_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_209_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_209_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_209_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_209_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_210_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_210_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_210_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_210_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_210_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_210_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_210_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_210_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_211_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_211_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_211_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_211_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_211_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_211_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_211_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_211_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_212_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_212_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_212_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_212_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_212_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_212_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_212_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_212_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_213_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_213_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_213_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_213_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_213_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_213_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_213_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_213_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_214_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_214_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_214_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_214_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_214_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_214_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_214_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_214_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_215_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_215_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_215_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_215_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_215_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_215_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_215_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_215_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_216_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_216_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_216_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_216_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_216_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_216_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_216_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_216_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_217_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_217_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_217_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_217_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_217_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_217_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_217_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_217_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_218_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_218_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_218_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_218_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_218_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_218_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_218_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_218_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_219_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_219_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_219_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_219_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_219_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_219_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_219_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_219_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_220_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_220_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_220_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_220_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_220_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_220_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_220_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_220_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_221_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_221_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_221_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_221_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_221_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_221_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_221_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_221_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_222_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_222_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_222_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_222_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_222_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_222_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_222_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_222_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_223_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_223_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_223_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_223_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_223_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_223_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_223_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_223_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_224_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_224_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_224_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_224_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_224_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_224_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_224_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_224_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_225_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_225_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_225_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_225_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_225_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_225_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_225_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_225_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_226_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_226_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_226_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_226_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_226_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_226_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_226_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_226_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_227_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_227_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_227_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_227_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_227_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_227_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_227_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_227_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_228_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_228_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_228_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_228_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_228_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_228_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_228_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_228_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_229_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_229_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_229_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_229_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_229_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_229_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_229_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_229_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_230_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_230_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_230_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_230_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_230_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_230_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_230_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_230_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_231_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_231_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_231_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_231_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_231_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_231_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_231_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_231_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_232_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_232_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_232_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_232_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_232_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_232_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_232_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_232_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_233_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_233_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_233_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_233_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_233_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_233_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_233_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_233_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_234_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_234_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_234_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_234_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_234_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_234_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_234_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_234_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_235_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_235_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_235_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_235_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_235_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_235_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_235_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_235_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_236_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_236_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_236_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_236_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_236_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_236_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_236_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_236_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_237_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_237_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_237_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_237_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_237_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_237_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_237_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_237_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_238_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_238_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_238_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_238_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_238_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_238_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_238_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_238_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_239_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_239_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_239_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_239_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_239_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_239_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_239_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_239_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_240_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_240_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_240_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_240_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_240_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_240_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_240_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_240_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_241_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_241_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_241_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_241_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_241_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_241_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_241_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_241_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_242_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_242_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_242_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_242_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_242_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_242_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_242_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_242_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_243_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_243_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_243_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_243_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_243_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_243_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_243_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_243_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_244_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_244_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_244_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_244_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_244_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_244_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_244_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_244_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_245_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_245_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_245_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_245_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_245_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_245_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_245_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_245_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_246_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_246_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_246_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_246_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_246_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_246_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_246_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_246_OFFSET 3

#define GICD_REGS_GICD_PRIORITY_INT3_247_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT3_247_OFFSET 27
#define GICD_REGS_GICD_PRIORITY_INT2_247_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT2_247_OFFSET 19
#define GICD_REGS_GICD_PRIORITY_INT1_247_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT1_247_OFFSET 11
#define GICD_REGS_GICD_PRIORITY_INT0_247_LEN    5
#define GICD_REGS_GICD_PRIORITY_INT0_247_OFFSET 3

#define GICD_REGS_GICD_LOW_TARGET_0_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_0_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_1_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_1_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_2_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_2_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_3_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_3_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_4_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_4_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_5_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_5_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_6_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_6_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_7_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_7_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_8_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_8_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_9_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_9_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_10_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_10_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_11_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_11_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_12_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_12_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_13_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_13_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_14_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_14_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_15_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_15_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_16_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_16_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_17_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_17_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_18_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_18_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_19_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_19_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_20_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_20_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_21_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_21_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_22_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_22_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_23_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_23_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_24_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_24_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_25_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_25_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_26_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_26_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_27_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_27_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_28_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_28_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_29_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_29_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_30_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_30_OFFSET 0

#define GICD_REGS_GICD_LOW_TARGET_31_LEN    32
#define GICD_REGS_GICD_LOW_TARGET_31_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_0_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_0_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_1_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_1_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_2_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_2_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_3_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_3_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_4_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_4_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_5_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_5_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_6_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_6_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_7_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_7_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_8_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_8_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_9_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_9_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_10_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_10_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_11_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_11_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_12_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_12_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_13_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_13_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_14_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_14_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_15_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_15_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_16_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_16_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_17_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_17_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_18_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_18_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_19_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_19_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_20_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_20_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_21_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_21_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_22_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_22_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_23_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_23_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_24_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_24_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_25_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_25_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_26_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_26_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_27_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_27_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_28_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_28_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_29_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_29_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_30_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_30_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_31_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_31_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_32_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_32_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_33_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_33_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_34_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_34_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_35_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_35_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_36_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_36_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_37_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_37_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_38_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_38_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_39_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_39_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_40_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_40_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_41_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_41_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_42_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_42_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_43_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_43_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_44_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_44_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_45_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_45_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_46_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_46_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_47_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_47_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_48_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_48_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_49_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_49_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_50_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_50_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_51_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_51_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_52_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_52_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_53_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_53_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_54_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_54_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_55_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_55_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_56_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_56_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_57_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_57_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_58_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_58_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_59_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_59_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_60_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_60_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_61_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_61_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_62_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_62_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_63_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_63_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_64_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_64_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_65_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_65_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_66_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_66_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_67_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_67_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_68_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_68_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_69_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_69_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_70_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_70_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_71_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_71_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_72_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_72_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_73_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_73_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_74_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_74_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_75_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_75_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_76_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_76_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_77_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_77_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_78_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_78_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_79_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_79_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_80_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_80_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_81_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_81_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_82_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_82_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_83_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_83_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_84_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_84_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_85_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_85_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_86_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_86_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_87_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_87_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_88_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_88_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_89_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_89_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_90_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_90_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_91_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_91_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_92_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_92_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_93_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_93_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_94_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_94_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_95_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_95_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_96_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_96_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_97_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_97_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_98_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_98_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_99_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_99_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_100_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_100_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_101_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_101_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_102_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_102_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_103_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_103_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_104_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_104_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_105_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_105_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_106_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_106_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_107_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_107_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_108_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_108_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_109_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_109_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_110_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_110_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_111_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_111_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_112_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_112_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_113_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_113_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_114_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_114_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_115_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_115_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_116_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_116_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_117_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_117_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_118_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_118_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_119_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_119_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_120_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_120_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_121_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_121_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_122_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_122_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_123_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_123_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_124_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_124_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_125_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_125_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_126_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_126_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_127_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_127_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_128_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_128_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_129_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_129_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_130_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_130_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_131_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_131_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_132_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_132_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_133_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_133_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_134_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_134_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_135_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_135_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_136_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_136_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_137_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_137_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_138_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_138_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_139_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_139_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_140_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_140_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_141_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_141_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_142_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_142_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_143_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_143_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_144_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_144_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_145_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_145_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_146_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_146_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_147_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_147_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_148_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_148_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_149_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_149_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_150_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_150_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_151_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_151_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_152_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_152_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_153_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_153_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_154_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_154_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_155_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_155_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_156_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_156_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_157_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_157_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_158_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_158_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_159_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_159_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_160_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_160_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_161_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_161_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_162_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_162_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_163_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_163_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_164_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_164_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_165_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_165_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_166_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_166_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_167_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_167_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_168_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_168_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_169_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_169_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_170_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_170_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_171_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_171_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_172_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_172_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_173_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_173_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_174_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_174_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_175_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_175_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_176_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_176_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_177_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_177_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_178_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_178_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_179_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_179_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_180_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_180_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_181_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_181_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_182_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_182_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_183_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_183_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_184_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_184_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_185_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_185_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_186_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_186_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_187_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_187_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_188_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_188_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_189_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_189_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_190_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_190_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_191_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_191_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_192_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_192_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_193_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_193_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_194_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_194_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_195_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_195_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_196_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_196_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_197_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_197_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_198_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_198_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_199_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_199_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_200_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_200_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_201_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_201_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_202_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_202_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_203_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_203_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_204_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_204_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_205_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_205_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_206_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_206_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_207_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_207_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_208_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_208_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_209_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_209_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_210_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_210_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_211_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_211_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_212_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_212_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_213_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_213_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_214_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_214_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_215_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_215_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_216_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_216_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_217_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_217_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_218_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_218_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_219_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_219_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_220_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_220_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_221_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_221_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_222_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_222_OFFSET 0

#define GICD_REGS_GICD_SPI_TARGET_223_LEN    32
#define GICD_REGS_GICD_SPI_TARGET_223_OFFSET 0

#define GICD_REGS_GICD_SGICONFIG_LEN    32
#define GICD_REGS_GICD_SGICONFIG_OFFSET 0

#define GICD_REGS_GICD_PPICONFIG_LEN    32
#define GICD_REGS_GICD_PPICONFIG_OFFSET 0

#define GICD_REGS_GICD_NNSPI_CONFIG15_0_LEN    1
#define GICD_REGS_GICD_NNSPI_CONFIG15_0_OFFSET 31
#define GICD_REGS_GICD_NNSPI_CONFIG14_0_LEN    1
#define GICD_REGS_GICD_NNSPI_CONFIG14_0_OFFSET 29
#define GICD_REGS_GICD_NNSPI_CONFIG13_0_LEN    1
#define GICD_REGS_GICD_NNSPI_CONFIG13_0_OFFSET 27
#define GICD_REGS_GICD_NNSPI_CONFIG12_0_LEN    1
#define GICD_REGS_GICD_NNSPI_CONFIG12_0_OFFSET 25
#define GICD_REGS_GICD_NNSPI_CONFIG11_0_LEN    1
#define GICD_REGS_GICD_NNSPI_CONFIG11_0_OFFSET 23
#define GICD_REGS_GICD_NNSPI_CONFIG10_0_LEN    1
#define GICD_REGS_GICD_NNSPI_CONFIG10_0_OFFSET 21
#define GICD_REGS_GICD_NNSPI_CONFIG9_0_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG9_0_OFFSET  19
#define GICD_REGS_GICD_NNSPI_CONFIG8_0_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG8_0_OFFSET  17
#define GICD_REGS_GICD_NNSPI_CONFIG7_0_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG7_0_OFFSET  15
#define GICD_REGS_GICD_NNSPI_CONFIG6_0_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG6_0_OFFSET  13
#define GICD_REGS_GICD_NNSPI_CONFIG5_0_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG5_0_OFFSET  11
#define GICD_REGS_GICD_NNSPI_CONFIG4_0_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG4_0_OFFSET  9
#define GICD_REGS_GICD_NNSPI_CONFIG3_0_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG3_0_OFFSET  7
#define GICD_REGS_GICD_NNSPI_CONFIG2_0_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG2_0_OFFSET  5
#define GICD_REGS_GICD_NNSPI_CONFIG1_0_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG1_0_OFFSET  3
#define GICD_REGS_GICD_NNSPI_CONFIG0_0_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG0_0_OFFSET  1

#define GICD_REGS_GICD_NNSPI_CONFIG15_1_LEN    1
#define GICD_REGS_GICD_NNSPI_CONFIG15_1_OFFSET 31
#define GICD_REGS_GICD_NNSPI_CONFIG14_1_LEN    1
#define GICD_REGS_GICD_NNSPI_CONFIG14_1_OFFSET 29
#define GICD_REGS_GICD_NNSPI_CONFIG13_1_LEN    1
#define GICD_REGS_GICD_NNSPI_CONFIG13_1_OFFSET 27
#define GICD_REGS_GICD_NNSPI_CONFIG12_1_LEN    1
#define GICD_REGS_GICD_NNSPI_CONFIG12_1_OFFSET 25
#define GICD_REGS_GICD_NNSPI_CONFIG11_1_LEN    1
#define GICD_REGS_GICD_NNSPI_CONFIG11_1_OFFSET 23
#define GICD_REGS_GICD_NNSPI_CONFIG10_1_LEN    1
#define GICD_REGS_GICD_NNSPI_CONFIG10_1_OFFSET 21
#define GICD_REGS_GICD_NNSPI_CONFIG9_1_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG9_1_OFFSET  19
#define GICD_REGS_GICD_NNSPI_CONFIG8_1_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG8_1_OFFSET  17
#define GICD_REGS_GICD_NNSPI_CONFIG7_1_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG7_1_OFFSET  15
#define GICD_REGS_GICD_NNSPI_CONFIG6_1_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG6_1_OFFSET  13
#define GICD_REGS_GICD_NNSPI_CONFIG5_1_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG5_1_OFFSET  11
#define GICD_REGS_GICD_NNSPI_CONFIG4_1_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG4_1_OFFSET  9
#define GICD_REGS_GICD_NNSPI_CONFIG3_1_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG3_1_OFFSET  7
#define GICD_REGS_GICD_NNSPI_CONFIG2_1_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG2_1_OFFSET  5
#define GICD_REGS_GICD_NNSPI_CONFIG1_1_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG1_1_OFFSET  3
#define GICD_REGS_GICD_NNSPI_CONFIG0_1_LEN     1
#define GICD_REGS_GICD_NNSPI_CONFIG0_1_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_0_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_0_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_0_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_0_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_0_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_0_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_0_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_0_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_0_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_0_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_0_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_0_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_0_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_0_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_0_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_0_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_0_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_0_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_0_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_0_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_0_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_0_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_0_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_0_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_0_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_0_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_0_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_0_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_0_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_0_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_0_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_0_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_1_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_1_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_1_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_1_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_1_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_1_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_1_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_1_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_1_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_1_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_1_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_1_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_1_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_1_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_1_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_1_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_1_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_1_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_1_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_1_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_1_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_1_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_1_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_1_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_1_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_1_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_1_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_1_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_1_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_1_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_1_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_1_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_2_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_2_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_2_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_2_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_2_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_2_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_2_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_2_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_2_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_2_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_2_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_2_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_2_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_2_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_2_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_2_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_2_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_2_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_2_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_2_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_2_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_2_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_2_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_2_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_2_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_2_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_2_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_2_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_2_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_2_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_2_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_2_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_3_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_3_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_3_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_3_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_3_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_3_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_3_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_3_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_3_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_3_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_3_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_3_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_3_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_3_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_3_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_3_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_3_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_3_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_3_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_3_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_3_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_3_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_3_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_3_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_3_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_3_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_3_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_3_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_3_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_3_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_3_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_3_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_4_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_4_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_4_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_4_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_4_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_4_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_4_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_4_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_4_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_4_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_4_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_4_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_4_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_4_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_4_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_4_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_4_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_4_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_4_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_4_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_4_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_4_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_4_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_4_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_4_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_4_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_4_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_4_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_4_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_4_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_4_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_4_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_5_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_5_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_5_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_5_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_5_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_5_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_5_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_5_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_5_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_5_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_5_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_5_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_5_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_5_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_5_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_5_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_5_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_5_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_5_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_5_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_5_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_5_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_5_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_5_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_5_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_5_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_5_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_5_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_5_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_5_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_5_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_5_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_6_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_6_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_6_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_6_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_6_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_6_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_6_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_6_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_6_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_6_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_6_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_6_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_6_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_6_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_6_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_6_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_6_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_6_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_6_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_6_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_6_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_6_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_6_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_6_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_6_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_6_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_6_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_6_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_6_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_6_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_6_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_6_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_7_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_7_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_7_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_7_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_7_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_7_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_7_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_7_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_7_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_7_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_7_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_7_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_7_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_7_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_7_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_7_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_7_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_7_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_7_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_7_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_7_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_7_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_7_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_7_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_7_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_7_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_7_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_7_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_7_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_7_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_7_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_7_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_8_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_8_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_8_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_8_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_8_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_8_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_8_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_8_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_8_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_8_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_8_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_8_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_8_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_8_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_8_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_8_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_8_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_8_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_8_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_8_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_8_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_8_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_8_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_8_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_8_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_8_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_8_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_8_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_8_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_8_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_8_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_8_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_9_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_9_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_9_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_9_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_9_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_9_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_9_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_9_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_9_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_9_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_9_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_9_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_9_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_9_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_9_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_9_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_9_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_9_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_9_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_9_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_9_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_9_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_9_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_9_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_9_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_9_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_9_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_9_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_9_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_9_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_9_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_9_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_10_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_10_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_10_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_10_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_10_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_10_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_10_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_10_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_10_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_10_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_10_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_10_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_10_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_10_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_10_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_10_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_10_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_10_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_10_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_10_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_10_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_10_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_10_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_10_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_10_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_10_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_10_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_10_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_10_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_10_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_10_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_10_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_11_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_11_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_11_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_11_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_11_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_11_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_11_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_11_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_11_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_11_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_11_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_11_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_11_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_11_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_11_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_11_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_11_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_11_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_11_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_11_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_11_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_11_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_11_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_11_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_11_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_11_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_11_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_11_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_11_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_11_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_11_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_11_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_12_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_12_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_12_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_12_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_12_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_12_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_12_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_12_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_12_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_12_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_12_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_12_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_12_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_12_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_12_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_12_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_12_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_12_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_12_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_12_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_12_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_12_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_12_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_12_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_12_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_12_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_12_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_12_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_12_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_12_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_12_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_12_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_13_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_13_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_13_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_13_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_13_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_13_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_13_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_13_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_13_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_13_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_13_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_13_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_13_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_13_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_13_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_13_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_13_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_13_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_13_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_13_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_13_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_13_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_13_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_13_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_13_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_13_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_13_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_13_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_13_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_13_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_13_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_13_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_14_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_14_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_14_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_14_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_14_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_14_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_14_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_14_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_14_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_14_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_14_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_14_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_14_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_14_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_14_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_14_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_14_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_14_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_14_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_14_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_14_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_14_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_14_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_14_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_14_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_14_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_14_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_14_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_14_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_14_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_14_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_14_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_15_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_15_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_15_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_15_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_15_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_15_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_15_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_15_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_15_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_15_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_15_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_15_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_15_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_15_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_15_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_15_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_15_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_15_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_15_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_15_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_15_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_15_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_15_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_15_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_15_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_15_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_15_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_15_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_15_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_15_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_15_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_15_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_16_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_16_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_16_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_16_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_16_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_16_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_16_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_16_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_16_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_16_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_16_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_16_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_16_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_16_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_16_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_16_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_16_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_16_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_16_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_16_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_16_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_16_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_16_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_16_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_16_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_16_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_16_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_16_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_16_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_16_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_16_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_16_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_17_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_17_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_17_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_17_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_17_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_17_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_17_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_17_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_17_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_17_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_17_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_17_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_17_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_17_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_17_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_17_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_17_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_17_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_17_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_17_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_17_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_17_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_17_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_17_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_17_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_17_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_17_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_17_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_17_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_17_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_17_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_17_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_18_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_18_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_18_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_18_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_18_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_18_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_18_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_18_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_18_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_18_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_18_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_18_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_18_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_18_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_18_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_18_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_18_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_18_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_18_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_18_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_18_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_18_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_18_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_18_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_18_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_18_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_18_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_18_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_18_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_18_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_18_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_18_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_19_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_19_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_19_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_19_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_19_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_19_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_19_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_19_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_19_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_19_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_19_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_19_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_19_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_19_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_19_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_19_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_19_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_19_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_19_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_19_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_19_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_19_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_19_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_19_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_19_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_19_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_19_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_19_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_19_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_19_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_19_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_19_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_20_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_20_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_20_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_20_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_20_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_20_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_20_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_20_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_20_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_20_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_20_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_20_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_20_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_20_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_20_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_20_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_20_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_20_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_20_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_20_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_20_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_20_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_20_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_20_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_20_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_20_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_20_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_20_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_20_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_20_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_20_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_20_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_21_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_21_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_21_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_21_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_21_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_21_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_21_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_21_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_21_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_21_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_21_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_21_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_21_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_21_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_21_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_21_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_21_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_21_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_21_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_21_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_21_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_21_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_21_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_21_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_21_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_21_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_21_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_21_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_21_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_21_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_21_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_21_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_22_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_22_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_22_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_22_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_22_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_22_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_22_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_22_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_22_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_22_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_22_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_22_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_22_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_22_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_22_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_22_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_22_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_22_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_22_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_22_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_22_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_22_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_22_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_22_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_22_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_22_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_22_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_22_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_22_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_22_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_22_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_22_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_23_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_23_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_23_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_23_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_23_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_23_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_23_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_23_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_23_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_23_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_23_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_23_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_23_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_23_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_23_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_23_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_23_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_23_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_23_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_23_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_23_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_23_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_23_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_23_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_23_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_23_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_23_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_23_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_23_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_23_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_23_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_23_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_24_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_24_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_24_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_24_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_24_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_24_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_24_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_24_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_24_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_24_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_24_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_24_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_24_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_24_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_24_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_24_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_24_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_24_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_24_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_24_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_24_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_24_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_24_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_24_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_24_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_24_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_24_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_24_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_24_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_24_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_24_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_24_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_25_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_25_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_25_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_25_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_25_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_25_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_25_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_25_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_25_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_25_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_25_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_25_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_25_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_25_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_25_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_25_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_25_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_25_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_25_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_25_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_25_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_25_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_25_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_25_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_25_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_25_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_25_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_25_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_25_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_25_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_25_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_25_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_26_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_26_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_26_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_26_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_26_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_26_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_26_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_26_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_26_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_26_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_26_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_26_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_26_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_26_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_26_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_26_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_26_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_26_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_26_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_26_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_26_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_26_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_26_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_26_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_26_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_26_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_26_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_26_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_26_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_26_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_26_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_26_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_27_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_27_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_27_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_27_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_27_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_27_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_27_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_27_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_27_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_27_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_27_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_27_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_27_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_27_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_27_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_27_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_27_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_27_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_27_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_27_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_27_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_27_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_27_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_27_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_27_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_27_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_27_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_27_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_27_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_27_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_27_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_27_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_28_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_28_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_28_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_28_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_28_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_28_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_28_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_28_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_28_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_28_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_28_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_28_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_28_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_28_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_28_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_28_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_28_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_28_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_28_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_28_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_28_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_28_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_28_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_28_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_28_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_28_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_28_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_28_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_28_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_28_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_28_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_28_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_29_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_29_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_29_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_29_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_29_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_29_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_29_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_29_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_29_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_29_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_29_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_29_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_29_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_29_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_29_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_29_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_29_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_29_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_29_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_29_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_29_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_29_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_29_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_29_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_29_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_29_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_29_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_29_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_29_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_29_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_29_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_29_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_30_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_30_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_30_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_30_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_30_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_30_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_30_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_30_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_30_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_30_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_30_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_30_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_30_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_30_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_30_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_30_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_30_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_30_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_30_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_30_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_30_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_30_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_30_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_30_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_30_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_30_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_30_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_30_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_30_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_30_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_30_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_30_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_31_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_31_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_31_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_31_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_31_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_31_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_31_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_31_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_31_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_31_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_31_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_31_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_31_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_31_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_31_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_31_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_31_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_31_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_31_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_31_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_31_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_31_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_31_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_31_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_31_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_31_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_31_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_31_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_31_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_31_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_31_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_31_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_32_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_32_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_32_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_32_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_32_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_32_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_32_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_32_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_32_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_32_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_32_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_32_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_32_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_32_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_32_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_32_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_32_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_32_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_32_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_32_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_32_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_32_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_32_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_32_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_32_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_32_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_32_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_32_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_32_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_32_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_32_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_32_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_33_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_33_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_33_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_33_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_33_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_33_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_33_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_33_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_33_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_33_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_33_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_33_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_33_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_33_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_33_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_33_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_33_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_33_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_33_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_33_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_33_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_33_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_33_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_33_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_33_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_33_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_33_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_33_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_33_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_33_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_33_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_33_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_34_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_34_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_34_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_34_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_34_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_34_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_34_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_34_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_34_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_34_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_34_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_34_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_34_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_34_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_34_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_34_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_34_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_34_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_34_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_34_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_34_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_34_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_34_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_34_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_34_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_34_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_34_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_34_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_34_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_34_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_34_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_34_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_35_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_35_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_35_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_35_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_35_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_35_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_35_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_35_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_35_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_35_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_35_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_35_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_35_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_35_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_35_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_35_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_35_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_35_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_35_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_35_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_35_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_35_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_35_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_35_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_35_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_35_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_35_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_35_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_35_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_35_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_35_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_35_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_36_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_36_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_36_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_36_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_36_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_36_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_36_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_36_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_36_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_36_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_36_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_36_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_36_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_36_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_36_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_36_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_36_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_36_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_36_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_36_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_36_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_36_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_36_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_36_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_36_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_36_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_36_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_36_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_36_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_36_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_36_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_36_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_37_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_37_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_37_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_37_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_37_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_37_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_37_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_37_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_37_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_37_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_37_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_37_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_37_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_37_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_37_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_37_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_37_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_37_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_37_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_37_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_37_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_37_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_37_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_37_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_37_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_37_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_37_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_37_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_37_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_37_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_37_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_37_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_38_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_38_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_38_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_38_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_38_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_38_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_38_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_38_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_38_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_38_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_38_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_38_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_38_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_38_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_38_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_38_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_38_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_38_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_38_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_38_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_38_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_38_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_38_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_38_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_38_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_38_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_38_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_38_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_38_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_38_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_38_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_38_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_39_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_39_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_39_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_39_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_39_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_39_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_39_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_39_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_39_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_39_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_39_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_39_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_39_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_39_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_39_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_39_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_39_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_39_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_39_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_39_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_39_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_39_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_39_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_39_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_39_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_39_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_39_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_39_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_39_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_39_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_39_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_39_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_40_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_40_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_40_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_40_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_40_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_40_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_40_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_40_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_40_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_40_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_40_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_40_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_40_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_40_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_40_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_40_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_40_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_40_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_40_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_40_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_40_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_40_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_40_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_40_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_40_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_40_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_40_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_40_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_40_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_40_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_40_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_40_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_41_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_41_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_41_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_41_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_41_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_41_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_41_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_41_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_41_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_41_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_41_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_41_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_41_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_41_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_41_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_41_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_41_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_41_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_41_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_41_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_41_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_41_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_41_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_41_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_41_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_41_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_41_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_41_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_41_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_41_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_41_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_41_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_42_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_42_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_42_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_42_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_42_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_42_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_42_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_42_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_42_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_42_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_42_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_42_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_42_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_42_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_42_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_42_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_42_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_42_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_42_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_42_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_42_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_42_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_42_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_42_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_42_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_42_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_42_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_42_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_42_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_42_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_42_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_42_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_43_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_43_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_43_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_43_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_43_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_43_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_43_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_43_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_43_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_43_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_43_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_43_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_43_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_43_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_43_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_43_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_43_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_43_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_43_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_43_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_43_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_43_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_43_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_43_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_43_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_43_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_43_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_43_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_43_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_43_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_43_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_43_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_44_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_44_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_44_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_44_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_44_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_44_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_44_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_44_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_44_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_44_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_44_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_44_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_44_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_44_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_44_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_44_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_44_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_44_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_44_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_44_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_44_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_44_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_44_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_44_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_44_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_44_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_44_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_44_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_44_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_44_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_44_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_44_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_45_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_45_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_45_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_45_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_45_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_45_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_45_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_45_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_45_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_45_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_45_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_45_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_45_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_45_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_45_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_45_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_45_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_45_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_45_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_45_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_45_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_45_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_45_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_45_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_45_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_45_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_45_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_45_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_45_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_45_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_45_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_45_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_46_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_46_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_46_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_46_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_46_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_46_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_46_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_46_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_46_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_46_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_46_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_46_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_46_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_46_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_46_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_46_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_46_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_46_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_46_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_46_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_46_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_46_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_46_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_46_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_46_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_46_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_46_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_46_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_46_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_46_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_46_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_46_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_47_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_47_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_47_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_47_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_47_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_47_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_47_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_47_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_47_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_47_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_47_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_47_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_47_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_47_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_47_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_47_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_47_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_47_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_47_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_47_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_47_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_47_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_47_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_47_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_47_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_47_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_47_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_47_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_47_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_47_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_47_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_47_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_48_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_48_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_48_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_48_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_48_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_48_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_48_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_48_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_48_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_48_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_48_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_48_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_48_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_48_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_48_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_48_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_48_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_48_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_48_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_48_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_48_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_48_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_48_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_48_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_48_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_48_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_48_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_48_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_48_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_48_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_48_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_48_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_49_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_49_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_49_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_49_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_49_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_49_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_49_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_49_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_49_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_49_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_49_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_49_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_49_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_49_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_49_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_49_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_49_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_49_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_49_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_49_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_49_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_49_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_49_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_49_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_49_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_49_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_49_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_49_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_49_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_49_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_49_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_49_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_50_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_50_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_50_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_50_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_50_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_50_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_50_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_50_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_50_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_50_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_50_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_50_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_50_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_50_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_50_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_50_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_50_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_50_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_50_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_50_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_50_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_50_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_50_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_50_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_50_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_50_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_50_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_50_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_50_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_50_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_50_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_50_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_51_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_51_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_51_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_51_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_51_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_51_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_51_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_51_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_51_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_51_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_51_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_51_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_51_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_51_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_51_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_51_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_51_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_51_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_51_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_51_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_51_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_51_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_51_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_51_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_51_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_51_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_51_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_51_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_51_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_51_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_51_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_51_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_52_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_52_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_52_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_52_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_52_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_52_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_52_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_52_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_52_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_52_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_52_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_52_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_52_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_52_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_52_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_52_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_52_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_52_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_52_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_52_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_52_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_52_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_52_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_52_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_52_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_52_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_52_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_52_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_52_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_52_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_52_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_52_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_53_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_53_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_53_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_53_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_53_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_53_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_53_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_53_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_53_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_53_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_53_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_53_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_53_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_53_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_53_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_53_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_53_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_53_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_53_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_53_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_53_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_53_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_53_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_53_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_53_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_53_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_53_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_53_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_53_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_53_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_53_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_53_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_54_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_54_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_54_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_54_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_54_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_54_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_54_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_54_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_54_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_54_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_54_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_54_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_54_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_54_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_54_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_54_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_54_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_54_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_54_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_54_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_54_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_54_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_54_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_54_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_54_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_54_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_54_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_54_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_54_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_54_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_54_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_54_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_55_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_55_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_55_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_55_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_55_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_55_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_55_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_55_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_55_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_55_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_55_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_55_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_55_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_55_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_55_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_55_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_55_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_55_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_55_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_55_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_55_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_55_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_55_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_55_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_55_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_55_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_55_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_55_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_55_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_55_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_55_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_55_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_56_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_56_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_56_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_56_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_56_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_56_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_56_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_56_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_56_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_56_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_56_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_56_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_56_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_56_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_56_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_56_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_56_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_56_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_56_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_56_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_56_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_56_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_56_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_56_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_56_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_56_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_56_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_56_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_56_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_56_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_56_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_56_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_57_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_57_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_57_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_57_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_57_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_57_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_57_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_57_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_57_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_57_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_57_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_57_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_57_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_57_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_57_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_57_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_57_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_57_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_57_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_57_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_57_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_57_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_57_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_57_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_57_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_57_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_57_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_57_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_57_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_57_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_57_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_57_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_58_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_58_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_58_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_58_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_58_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_58_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_58_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_58_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_58_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_58_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_58_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_58_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_58_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_58_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_58_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_58_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_58_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_58_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_58_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_58_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_58_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_58_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_58_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_58_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_58_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_58_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_58_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_58_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_58_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_58_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_58_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_58_OFFSET  1

#define GICD_REGS_GICD_SPI_CONFIG15_59_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG15_59_OFFSET 31
#define GICD_REGS_GICD_SPI_CONFIG14_59_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG14_59_OFFSET 29
#define GICD_REGS_GICD_SPI_CONFIG13_59_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG13_59_OFFSET 27
#define GICD_REGS_GICD_SPI_CONFIG12_59_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG12_59_OFFSET 25
#define GICD_REGS_GICD_SPI_CONFIG11_59_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG11_59_OFFSET 23
#define GICD_REGS_GICD_SPI_CONFIG10_59_LEN    1
#define GICD_REGS_GICD_SPI_CONFIG10_59_OFFSET 21
#define GICD_REGS_GICD_SPI_CONFIG9_59_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG9_59_OFFSET  19
#define GICD_REGS_GICD_SPI_CONFIG8_59_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG8_59_OFFSET  17
#define GICD_REGS_GICD_SPI_CONFIG7_59_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG7_59_OFFSET  15
#define GICD_REGS_GICD_SPI_CONFIG6_59_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG6_59_OFFSET  13
#define GICD_REGS_GICD_SPI_CONFIG5_59_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG5_59_OFFSET  11
#define GICD_REGS_GICD_SPI_CONFIG4_59_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG4_59_OFFSET  9
#define GICD_REGS_GICD_SPI_CONFIG3_59_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG3_59_OFFSET  7
#define GICD_REGS_GICD_SPI_CONFIG2_59_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG2_59_OFFSET  5
#define GICD_REGS_GICD_SPI_CONFIG1_59_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG1_59_OFFSET  3
#define GICD_REGS_GICD_SPI_CONFIG0_59_LEN     1
#define GICD_REGS_GICD_SPI_CONFIG0_59_OFFSET  1

#define GICD_REGS_GICD_PPIMODE_LEN    12
#define GICD_REGS_GICD_PPIMODE_OFFSET 20
#define GICD_REGS_GICD_SGIMODE_LEN    16
#define GICD_REGS_GICD_SGIMODE_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_0_LEN    32
#define GICD_REGS_GICD_SPIMODE_0_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_1_LEN    32
#define GICD_REGS_GICD_SPIMODE_1_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_2_LEN    32
#define GICD_REGS_GICD_SPIMODE_2_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_3_LEN    32
#define GICD_REGS_GICD_SPIMODE_3_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_4_LEN    32
#define GICD_REGS_GICD_SPIMODE_4_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_5_LEN    32
#define GICD_REGS_GICD_SPIMODE_5_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_6_LEN    32
#define GICD_REGS_GICD_SPIMODE_6_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_7_LEN    32
#define GICD_REGS_GICD_SPIMODE_7_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_8_LEN    32
#define GICD_REGS_GICD_SPIMODE_8_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_9_LEN    32
#define GICD_REGS_GICD_SPIMODE_9_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_10_LEN    32
#define GICD_REGS_GICD_SPIMODE_10_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_11_LEN    32
#define GICD_REGS_GICD_SPIMODE_11_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_12_LEN    32
#define GICD_REGS_GICD_SPIMODE_12_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_13_LEN    32
#define GICD_REGS_GICD_SPIMODE_13_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_14_LEN    32
#define GICD_REGS_GICD_SPIMODE_14_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_15_LEN    32
#define GICD_REGS_GICD_SPIMODE_15_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_16_LEN    32
#define GICD_REGS_GICD_SPIMODE_16_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_17_LEN    32
#define GICD_REGS_GICD_SPIMODE_17_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_18_LEN    32
#define GICD_REGS_GICD_SPIMODE_18_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_19_LEN    32
#define GICD_REGS_GICD_SPIMODE_19_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_20_LEN    32
#define GICD_REGS_GICD_SPIMODE_20_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_21_LEN    32
#define GICD_REGS_GICD_SPIMODE_21_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_22_LEN    32
#define GICD_REGS_GICD_SPIMODE_22_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_23_LEN    32
#define GICD_REGS_GICD_SPIMODE_23_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_24_LEN    32
#define GICD_REGS_GICD_SPIMODE_24_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_25_LEN    32
#define GICD_REGS_GICD_SPIMODE_25_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_26_LEN    32
#define GICD_REGS_GICD_SPIMODE_26_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_27_LEN    32
#define GICD_REGS_GICD_SPIMODE_27_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_28_LEN    32
#define GICD_REGS_GICD_SPIMODE_28_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_29_LEN    32
#define GICD_REGS_GICD_SPIMODE_29_OFFSET 0

#define GICD_REGS_GICD_SPIMODE_30_LEN    32
#define GICD_REGS_GICD_SPIMODE_30_OFFSET 0

#define GICD_REGS_GICD_NSAC_0_LEN    32
#define GICD_REGS_GICD_NSAC_0_OFFSET 0

#define GICD_REGS_GICD_NSAC_1_LEN    32
#define GICD_REGS_GICD_NSAC_1_OFFSET 0

#define GICD_REGS_GICD_NSAC_2_LEN    32
#define GICD_REGS_GICD_NSAC_2_OFFSET 0

#define GICD_REGS_GICD_NSAC_3_LEN    32
#define GICD_REGS_GICD_NSAC_3_OFFSET 0

#define GICD_REGS_GICD_NSAC_4_LEN    32
#define GICD_REGS_GICD_NSAC_4_OFFSET 0

#define GICD_REGS_GICD_NSAC_5_LEN    32
#define GICD_REGS_GICD_NSAC_5_OFFSET 0

#define GICD_REGS_GICD_NSAC_6_LEN    32
#define GICD_REGS_GICD_NSAC_6_OFFSET 0

#define GICD_REGS_GICD_NSAC_7_LEN    32
#define GICD_REGS_GICD_NSAC_7_OFFSET 0

#define GICD_REGS_GICD_NSAC_8_LEN    32
#define GICD_REGS_GICD_NSAC_8_OFFSET 0

#define GICD_REGS_GICD_NSAC_9_LEN    32
#define GICD_REGS_GICD_NSAC_9_OFFSET 0

#define GICD_REGS_GICD_NSAC_10_LEN    32
#define GICD_REGS_GICD_NSAC_10_OFFSET 0

#define GICD_REGS_GICD_NSAC_11_LEN    32
#define GICD_REGS_GICD_NSAC_11_OFFSET 0

#define GICD_REGS_GICD_NSAC_12_LEN    32
#define GICD_REGS_GICD_NSAC_12_OFFSET 0

#define GICD_REGS_GICD_NSAC_13_LEN    32
#define GICD_REGS_GICD_NSAC_13_OFFSET 0

#define GICD_REGS_GICD_NSAC_14_LEN    32
#define GICD_REGS_GICD_NSAC_14_OFFSET 0

#define GICD_REGS_GICD_NSAC_15_LEN    32
#define GICD_REGS_GICD_NSAC_15_OFFSET 0

#define GICD_REGS_GICD_NSAC_16_LEN    32
#define GICD_REGS_GICD_NSAC_16_OFFSET 0

#define GICD_REGS_GICD_NSAC_17_LEN    32
#define GICD_REGS_GICD_NSAC_17_OFFSET 0

#define GICD_REGS_GICD_NSAC_18_LEN    32
#define GICD_REGS_GICD_NSAC_18_OFFSET 0

#define GICD_REGS_GICD_NSAC_19_LEN    32
#define GICD_REGS_GICD_NSAC_19_OFFSET 0

#define GICD_REGS_GICD_NSAC_20_LEN    32
#define GICD_REGS_GICD_NSAC_20_OFFSET 0

#define GICD_REGS_GICD_NSAC_21_LEN    32
#define GICD_REGS_GICD_NSAC_21_OFFSET 0

#define GICD_REGS_GICD_NSAC_22_LEN    32
#define GICD_REGS_GICD_NSAC_22_OFFSET 0

#define GICD_REGS_GICD_NSAC_23_LEN    32
#define GICD_REGS_GICD_NSAC_23_OFFSET 0

#define GICD_REGS_GICD_NSAC_24_LEN    32
#define GICD_REGS_GICD_NSAC_24_OFFSET 0

#define GICD_REGS_GICD_NSAC_25_LEN    32
#define GICD_REGS_GICD_NSAC_25_OFFSET 0

#define GICD_REGS_GICD_NSAC_26_LEN    32
#define GICD_REGS_GICD_NSAC_26_OFFSET 0

#define GICD_REGS_GICD_NSAC_27_LEN    32
#define GICD_REGS_GICD_NSAC_27_OFFSET 0

#define GICD_REGS_GICD_NSAC_28_LEN    32
#define GICD_REGS_GICD_NSAC_28_OFFSET 0

#define GICD_REGS_GICD_NSAC_29_LEN    32
#define GICD_REGS_GICD_NSAC_29_OFFSET 0

#define GICD_REGS_GICD_NSAC_30_LEN    32
#define GICD_REGS_GICD_NSAC_30_OFFSET 0

#define GICD_REGS_GICD_NSAC_31_LEN    32
#define GICD_REGS_GICD_NSAC_31_OFFSET 0

#define GICD_REGS_GICD_NSAC_32_LEN    32
#define GICD_REGS_GICD_NSAC_32_OFFSET 0

#define GICD_REGS_GICD_NSAC_33_LEN    32
#define GICD_REGS_GICD_NSAC_33_OFFSET 0

#define GICD_REGS_GICD_NSAC_34_LEN    32
#define GICD_REGS_GICD_NSAC_34_OFFSET 0

#define GICD_REGS_GICD_NSAC_35_LEN    32
#define GICD_REGS_GICD_NSAC_35_OFFSET 0

#define GICD_REGS_GICD_NSAC_36_LEN    32
#define GICD_REGS_GICD_NSAC_36_OFFSET 0

#define GICD_REGS_GICD_NSAC_37_LEN    32
#define GICD_REGS_GICD_NSAC_37_OFFSET 0

#define GICD_REGS_GICD_NSAC_38_LEN    32
#define GICD_REGS_GICD_NSAC_38_OFFSET 0

#define GICD_REGS_GICD_NSAC_39_LEN    32
#define GICD_REGS_GICD_NSAC_39_OFFSET 0

#define GICD_REGS_GICD_NSAC_40_LEN    32
#define GICD_REGS_GICD_NSAC_40_OFFSET 0

#define GICD_REGS_GICD_NSAC_41_LEN    32
#define GICD_REGS_GICD_NSAC_41_OFFSET 0

#define GICD_REGS_GICD_NSAC_42_LEN    32
#define GICD_REGS_GICD_NSAC_42_OFFSET 0

#define GICD_REGS_GICD_NSAC_43_LEN    32
#define GICD_REGS_GICD_NSAC_43_OFFSET 0

#define GICD_REGS_GICD_NSAC_44_LEN    32
#define GICD_REGS_GICD_NSAC_44_OFFSET 0

#define GICD_REGS_GICD_NSAC_45_LEN    32
#define GICD_REGS_GICD_NSAC_45_OFFSET 0

#define GICD_REGS_GICD_NSAC_46_LEN    32
#define GICD_REGS_GICD_NSAC_46_OFFSET 0

#define GICD_REGS_GICD_NSAC_47_LEN    32
#define GICD_REGS_GICD_NSAC_47_OFFSET 0

#define GICD_REGS_GICD_NSAC_48_LEN    32
#define GICD_REGS_GICD_NSAC_48_OFFSET 0

#define GICD_REGS_GICD_NSAC_49_LEN    32
#define GICD_REGS_GICD_NSAC_49_OFFSET 0

#define GICD_REGS_GICD_NSAC_50_LEN    32
#define GICD_REGS_GICD_NSAC_50_OFFSET 0

#define GICD_REGS_GICD_NSAC_51_LEN    32
#define GICD_REGS_GICD_NSAC_51_OFFSET 0

#define GICD_REGS_GICD_NSAC_52_LEN    32
#define GICD_REGS_GICD_NSAC_52_OFFSET 0

#define GICD_REGS_GICD_NSAC_53_LEN    32
#define GICD_REGS_GICD_NSAC_53_OFFSET 0

#define GICD_REGS_GICD_NSAC_54_LEN    32
#define GICD_REGS_GICD_NSAC_54_OFFSET 0

#define GICD_REGS_GICD_NSAC_55_LEN    32
#define GICD_REGS_GICD_NSAC_55_OFFSET 0

#define GICD_REGS_GICD_NSAC_56_LEN    32
#define GICD_REGS_GICD_NSAC_56_OFFSET 0

#define GICD_REGS_GICD_NSAC_57_LEN    32
#define GICD_REGS_GICD_NSAC_57_OFFSET 0

#define GICD_REGS_GICD_NSAC_58_LEN    32
#define GICD_REGS_GICD_NSAC_58_OFFSET 0

#define GICD_REGS_GICD_NSAC_59_LEN    32
#define GICD_REGS_GICD_NSAC_59_OFFSET 0

#define GICD_REGS_GICD_NSAC_60_LEN    32
#define GICD_REGS_GICD_NSAC_60_OFFSET 0

#define GICD_REGS_GICD_NSAC_61_LEN    32
#define GICD_REGS_GICD_NSAC_61_OFFSET 0

#define GICD_REGS_GICD_NSAC_62_LEN    32
#define GICD_REGS_GICD_NSAC_62_OFFSET 0

#define GICD_REGS_GICD_NSAC_63_LEN    32
#define GICD_REGS_GICD_NSAC_63_OFFSET 0

#define GICD_REGS_GICD_FILTER_LEN        2
#define GICD_REGS_GICD_FILTER_OFFSET     24
#define GICD_REGS_GICD_TARGETLIST_LEN    16
#define GICD_REGS_GICD_TARGETLIST_OFFSET 8
#define GICD_REGS_NSATT_LEN              1
#define GICD_REGS_NSATT_OFFSET           7
#define GICD_REGS_GICD_SGIID_LEN         4
#define GICD_REGS_GICD_SGIID_OFFSET      0

#define GICD_REGS_GICD_CLEARPENDING_0_LEN    32
#define GICD_REGS_GICD_CLEARPENDING_0_OFFSET 0

#define GICD_REGS_GICD_CLEARPENDING_1_LEN    32
#define GICD_REGS_GICD_CLEARPENDING_1_OFFSET 0

#define GICD_REGS_GICD_CLEARPENDING_2_LEN    32
#define GICD_REGS_GICD_CLEARPENDING_2_OFFSET 0

#define GICD_REGS_GICD_CLEARPENDING_3_LEN    32
#define GICD_REGS_GICD_CLEARPENDING_3_OFFSET 0

#define GICD_REGS_GICD_CLEARPENDING_4_LEN    32
#define GICD_REGS_GICD_CLEARPENDING_4_OFFSET 0

#define GICD_REGS_GICD_CLEARPENDING_5_LEN    32
#define GICD_REGS_GICD_CLEARPENDING_5_OFFSET 0

#define GICD_REGS_GICD_CLEARPENDING_6_LEN    32
#define GICD_REGS_GICD_CLEARPENDING_6_OFFSET 0

#define GICD_REGS_GICD_CLEARPENDING_7_LEN    32
#define GICD_REGS_GICD_CLEARPENDING_7_OFFSET 0

#define GICD_REGS_GICD_SETPENDING_0_LEN    32
#define GICD_REGS_GICD_SETPENDING_0_OFFSET 0

#define GICD_REGS_GICD_SETPENDING_1_LEN    32
#define GICD_REGS_GICD_SETPENDING_1_OFFSET 0

#define GICD_REGS_GICD_SETPENDING_2_LEN    32
#define GICD_REGS_GICD_SETPENDING_2_OFFSET 0

#define GICD_REGS_GICD_SETPENDING_3_LEN    32
#define GICD_REGS_GICD_SETPENDING_3_OFFSET 0

#define GICD_REGS_GICD_SETPENDING_4_LEN    32
#define GICD_REGS_GICD_SETPENDING_4_OFFSET 0

#define GICD_REGS_GICD_SETPENDING_5_LEN    32
#define GICD_REGS_GICD_SETPENDING_5_OFFSET 0

#define GICD_REGS_GICD_SETPENDING_6_LEN    32
#define GICD_REGS_GICD_SETPENDING_6_OFFSET 0

#define GICD_REGS_GICD_SETPENDING_7_LEN    32
#define GICD_REGS_GICD_SETPENDING_7_OFFSET 0

#define GICD_REGS_GICD_IRM_0_LEN          1
#define GICD_REGS_GICD_IRM_0_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_0_LEN    8
#define GICD_REGS_GICD_AFFINITY2_0_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_0_LEN    8
#define GICD_REGS_GICD_AFFINITY1_0_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_0_LEN    8
#define GICD_REGS_GICD_AFFINITY0_0_OFFSET 0

#define GICD_REGS_GICD_IRM_1_LEN          1
#define GICD_REGS_GICD_IRM_1_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1_OFFSET 0

#define GICD_REGS_GICD_IRM_2_LEN          1
#define GICD_REGS_GICD_IRM_2_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_2_LEN    8
#define GICD_REGS_GICD_AFFINITY2_2_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_2_LEN    8
#define GICD_REGS_GICD_AFFINITY1_2_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_2_LEN    8
#define GICD_REGS_GICD_AFFINITY0_2_OFFSET 0

#define GICD_REGS_GICD_IRM_3_LEN          1
#define GICD_REGS_GICD_IRM_3_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_3_LEN    8
#define GICD_REGS_GICD_AFFINITY2_3_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_3_LEN    8
#define GICD_REGS_GICD_AFFINITY1_3_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_3_LEN    8
#define GICD_REGS_GICD_AFFINITY0_3_OFFSET 0

#define GICD_REGS_GICD_IRM_4_LEN          1
#define GICD_REGS_GICD_IRM_4_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_4_LEN    8
#define GICD_REGS_GICD_AFFINITY2_4_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_4_LEN    8
#define GICD_REGS_GICD_AFFINITY1_4_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_4_LEN    8
#define GICD_REGS_GICD_AFFINITY0_4_OFFSET 0

#define GICD_REGS_GICD_IRM_5_LEN          1
#define GICD_REGS_GICD_IRM_5_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_5_LEN    8
#define GICD_REGS_GICD_AFFINITY2_5_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_5_LEN    8
#define GICD_REGS_GICD_AFFINITY1_5_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_5_LEN    8
#define GICD_REGS_GICD_AFFINITY0_5_OFFSET 0

#define GICD_REGS_GICD_IRM_6_LEN          1
#define GICD_REGS_GICD_IRM_6_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_6_LEN    8
#define GICD_REGS_GICD_AFFINITY2_6_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_6_LEN    8
#define GICD_REGS_GICD_AFFINITY1_6_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_6_LEN    8
#define GICD_REGS_GICD_AFFINITY0_6_OFFSET 0

#define GICD_REGS_GICD_IRM_7_LEN          1
#define GICD_REGS_GICD_IRM_7_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_7_LEN    8
#define GICD_REGS_GICD_AFFINITY2_7_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_7_LEN    8
#define GICD_REGS_GICD_AFFINITY1_7_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_7_LEN    8
#define GICD_REGS_GICD_AFFINITY0_7_OFFSET 0

#define GICD_REGS_GICD_IRM_8_LEN          1
#define GICD_REGS_GICD_IRM_8_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_8_LEN    8
#define GICD_REGS_GICD_AFFINITY2_8_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_8_LEN    8
#define GICD_REGS_GICD_AFFINITY1_8_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_8_LEN    8
#define GICD_REGS_GICD_AFFINITY0_8_OFFSET 0

#define GICD_REGS_GICD_IRM_9_LEN          1
#define GICD_REGS_GICD_IRM_9_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_9_LEN    8
#define GICD_REGS_GICD_AFFINITY2_9_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_9_LEN    8
#define GICD_REGS_GICD_AFFINITY1_9_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_9_LEN    8
#define GICD_REGS_GICD_AFFINITY0_9_OFFSET 0

#define GICD_REGS_GICD_IRM_10_LEN          1
#define GICD_REGS_GICD_IRM_10_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_10_LEN    8
#define GICD_REGS_GICD_AFFINITY2_10_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_10_LEN    8
#define GICD_REGS_GICD_AFFINITY1_10_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_10_LEN    8
#define GICD_REGS_GICD_AFFINITY0_10_OFFSET 0

#define GICD_REGS_GICD_IRM_11_LEN          1
#define GICD_REGS_GICD_IRM_11_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_11_LEN    8
#define GICD_REGS_GICD_AFFINITY2_11_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_11_LEN    8
#define GICD_REGS_GICD_AFFINITY1_11_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_11_LEN    8
#define GICD_REGS_GICD_AFFINITY0_11_OFFSET 0

#define GICD_REGS_GICD_IRM_12_LEN          1
#define GICD_REGS_GICD_IRM_12_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_12_LEN    8
#define GICD_REGS_GICD_AFFINITY2_12_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_12_LEN    8
#define GICD_REGS_GICD_AFFINITY1_12_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_12_LEN    8
#define GICD_REGS_GICD_AFFINITY0_12_OFFSET 0

#define GICD_REGS_GICD_IRM_13_LEN          1
#define GICD_REGS_GICD_IRM_13_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_13_LEN    8
#define GICD_REGS_GICD_AFFINITY2_13_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_13_LEN    8
#define GICD_REGS_GICD_AFFINITY1_13_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_13_LEN    8
#define GICD_REGS_GICD_AFFINITY0_13_OFFSET 0

#define GICD_REGS_GICD_IRM_14_LEN          1
#define GICD_REGS_GICD_IRM_14_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_14_LEN    8
#define GICD_REGS_GICD_AFFINITY2_14_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_14_LEN    8
#define GICD_REGS_GICD_AFFINITY1_14_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_14_LEN    8
#define GICD_REGS_GICD_AFFINITY0_14_OFFSET 0

#define GICD_REGS_GICD_IRM_15_LEN          1
#define GICD_REGS_GICD_IRM_15_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_15_LEN    8
#define GICD_REGS_GICD_AFFINITY2_15_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_15_LEN    8
#define GICD_REGS_GICD_AFFINITY1_15_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_15_LEN    8
#define GICD_REGS_GICD_AFFINITY0_15_OFFSET 0

#define GICD_REGS_GICD_IRM_16_LEN          1
#define GICD_REGS_GICD_IRM_16_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_16_LEN    8
#define GICD_REGS_GICD_AFFINITY2_16_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_16_LEN    8
#define GICD_REGS_GICD_AFFINITY1_16_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_16_LEN    8
#define GICD_REGS_GICD_AFFINITY0_16_OFFSET 0

#define GICD_REGS_GICD_IRM_17_LEN          1
#define GICD_REGS_GICD_IRM_17_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_17_LEN    8
#define GICD_REGS_GICD_AFFINITY2_17_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_17_LEN    8
#define GICD_REGS_GICD_AFFINITY1_17_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_17_LEN    8
#define GICD_REGS_GICD_AFFINITY0_17_OFFSET 0

#define GICD_REGS_GICD_IRM_18_LEN          1
#define GICD_REGS_GICD_IRM_18_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_18_LEN    8
#define GICD_REGS_GICD_AFFINITY2_18_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_18_LEN    8
#define GICD_REGS_GICD_AFFINITY1_18_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_18_LEN    8
#define GICD_REGS_GICD_AFFINITY0_18_OFFSET 0

#define GICD_REGS_GICD_IRM_19_LEN          1
#define GICD_REGS_GICD_IRM_19_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_19_LEN    8
#define GICD_REGS_GICD_AFFINITY2_19_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_19_LEN    8
#define GICD_REGS_GICD_AFFINITY1_19_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_19_LEN    8
#define GICD_REGS_GICD_AFFINITY0_19_OFFSET 0

#define GICD_REGS_GICD_IRM_20_LEN          1
#define GICD_REGS_GICD_IRM_20_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_20_LEN    8
#define GICD_REGS_GICD_AFFINITY2_20_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_20_LEN    8
#define GICD_REGS_GICD_AFFINITY1_20_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_20_LEN    8
#define GICD_REGS_GICD_AFFINITY0_20_OFFSET 0

#define GICD_REGS_GICD_IRM_21_LEN          1
#define GICD_REGS_GICD_IRM_21_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_21_LEN    8
#define GICD_REGS_GICD_AFFINITY2_21_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_21_LEN    8
#define GICD_REGS_GICD_AFFINITY1_21_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_21_LEN    8
#define GICD_REGS_GICD_AFFINITY0_21_OFFSET 0

#define GICD_REGS_GICD_IRM_22_LEN          1
#define GICD_REGS_GICD_IRM_22_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_22_LEN    8
#define GICD_REGS_GICD_AFFINITY2_22_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_22_LEN    8
#define GICD_REGS_GICD_AFFINITY1_22_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_22_LEN    8
#define GICD_REGS_GICD_AFFINITY0_22_OFFSET 0

#define GICD_REGS_GICD_IRM_23_LEN          1
#define GICD_REGS_GICD_IRM_23_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_23_LEN    8
#define GICD_REGS_GICD_AFFINITY2_23_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_23_LEN    8
#define GICD_REGS_GICD_AFFINITY1_23_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_23_LEN    8
#define GICD_REGS_GICD_AFFINITY0_23_OFFSET 0

#define GICD_REGS_GICD_IRM_24_LEN          1
#define GICD_REGS_GICD_IRM_24_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_24_LEN    8
#define GICD_REGS_GICD_AFFINITY2_24_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_24_LEN    8
#define GICD_REGS_GICD_AFFINITY1_24_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_24_LEN    8
#define GICD_REGS_GICD_AFFINITY0_24_OFFSET 0

#define GICD_REGS_GICD_IRM_25_LEN          1
#define GICD_REGS_GICD_IRM_25_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_25_LEN    8
#define GICD_REGS_GICD_AFFINITY2_25_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_25_LEN    8
#define GICD_REGS_GICD_AFFINITY1_25_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_25_LEN    8
#define GICD_REGS_GICD_AFFINITY0_25_OFFSET 0

#define GICD_REGS_GICD_IRM_26_LEN          1
#define GICD_REGS_GICD_IRM_26_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_26_LEN    8
#define GICD_REGS_GICD_AFFINITY2_26_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_26_LEN    8
#define GICD_REGS_GICD_AFFINITY1_26_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_26_LEN    8
#define GICD_REGS_GICD_AFFINITY0_26_OFFSET 0

#define GICD_REGS_GICD_IRM_27_LEN          1
#define GICD_REGS_GICD_IRM_27_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_27_LEN    8
#define GICD_REGS_GICD_AFFINITY2_27_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_27_LEN    8
#define GICD_REGS_GICD_AFFINITY1_27_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_27_LEN    8
#define GICD_REGS_GICD_AFFINITY0_27_OFFSET 0

#define GICD_REGS_GICD_IRM_28_LEN          1
#define GICD_REGS_GICD_IRM_28_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_28_LEN    8
#define GICD_REGS_GICD_AFFINITY2_28_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_28_LEN    8
#define GICD_REGS_GICD_AFFINITY1_28_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_28_LEN    8
#define GICD_REGS_GICD_AFFINITY0_28_OFFSET 0

#define GICD_REGS_GICD_IRM_29_LEN          1
#define GICD_REGS_GICD_IRM_29_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_29_LEN    8
#define GICD_REGS_GICD_AFFINITY2_29_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_29_LEN    8
#define GICD_REGS_GICD_AFFINITY1_29_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_29_LEN    8
#define GICD_REGS_GICD_AFFINITY0_29_OFFSET 0

#define GICD_REGS_GICD_IRM_30_LEN          1
#define GICD_REGS_GICD_IRM_30_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_30_LEN    8
#define GICD_REGS_GICD_AFFINITY2_30_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_30_LEN    8
#define GICD_REGS_GICD_AFFINITY1_30_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_30_LEN    8
#define GICD_REGS_GICD_AFFINITY0_30_OFFSET 0

#define GICD_REGS_GICD_IRM_31_LEN          1
#define GICD_REGS_GICD_IRM_31_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_31_LEN    8
#define GICD_REGS_GICD_AFFINITY2_31_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_31_LEN    8
#define GICD_REGS_GICD_AFFINITY1_31_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_31_LEN    8
#define GICD_REGS_GICD_AFFINITY0_31_OFFSET 0

#define GICD_REGS_GICD_IRM_32_LEN          1
#define GICD_REGS_GICD_IRM_32_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_32_LEN    8
#define GICD_REGS_GICD_AFFINITY2_32_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_32_LEN    8
#define GICD_REGS_GICD_AFFINITY1_32_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_32_LEN    8
#define GICD_REGS_GICD_AFFINITY0_32_OFFSET 0

#define GICD_REGS_GICD_IRM_33_LEN          1
#define GICD_REGS_GICD_IRM_33_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_33_LEN    8
#define GICD_REGS_GICD_AFFINITY2_33_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_33_LEN    8
#define GICD_REGS_GICD_AFFINITY1_33_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_33_LEN    8
#define GICD_REGS_GICD_AFFINITY0_33_OFFSET 0

#define GICD_REGS_GICD_IRM_34_LEN          1
#define GICD_REGS_GICD_IRM_34_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_34_LEN    8
#define GICD_REGS_GICD_AFFINITY2_34_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_34_LEN    8
#define GICD_REGS_GICD_AFFINITY1_34_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_34_LEN    8
#define GICD_REGS_GICD_AFFINITY0_34_OFFSET 0

#define GICD_REGS_GICD_IRM_35_LEN          1
#define GICD_REGS_GICD_IRM_35_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_35_LEN    8
#define GICD_REGS_GICD_AFFINITY2_35_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_35_LEN    8
#define GICD_REGS_GICD_AFFINITY1_35_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_35_LEN    8
#define GICD_REGS_GICD_AFFINITY0_35_OFFSET 0

#define GICD_REGS_GICD_IRM_36_LEN          1
#define GICD_REGS_GICD_IRM_36_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_36_LEN    8
#define GICD_REGS_GICD_AFFINITY2_36_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_36_LEN    8
#define GICD_REGS_GICD_AFFINITY1_36_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_36_LEN    8
#define GICD_REGS_GICD_AFFINITY0_36_OFFSET 0

#define GICD_REGS_GICD_IRM_37_LEN          1
#define GICD_REGS_GICD_IRM_37_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_37_LEN    8
#define GICD_REGS_GICD_AFFINITY2_37_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_37_LEN    8
#define GICD_REGS_GICD_AFFINITY1_37_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_37_LEN    8
#define GICD_REGS_GICD_AFFINITY0_37_OFFSET 0

#define GICD_REGS_GICD_IRM_38_LEN          1
#define GICD_REGS_GICD_IRM_38_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_38_LEN    8
#define GICD_REGS_GICD_AFFINITY2_38_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_38_LEN    8
#define GICD_REGS_GICD_AFFINITY1_38_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_38_LEN    8
#define GICD_REGS_GICD_AFFINITY0_38_OFFSET 0

#define GICD_REGS_GICD_IRM_39_LEN          1
#define GICD_REGS_GICD_IRM_39_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_39_LEN    8
#define GICD_REGS_GICD_AFFINITY2_39_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_39_LEN    8
#define GICD_REGS_GICD_AFFINITY1_39_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_39_LEN    8
#define GICD_REGS_GICD_AFFINITY0_39_OFFSET 0

#define GICD_REGS_GICD_IRM_40_LEN          1
#define GICD_REGS_GICD_IRM_40_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_40_LEN    8
#define GICD_REGS_GICD_AFFINITY2_40_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_40_LEN    8
#define GICD_REGS_GICD_AFFINITY1_40_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_40_LEN    8
#define GICD_REGS_GICD_AFFINITY0_40_OFFSET 0

#define GICD_REGS_GICD_IRM_41_LEN          1
#define GICD_REGS_GICD_IRM_41_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_41_LEN    8
#define GICD_REGS_GICD_AFFINITY2_41_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_41_LEN    8
#define GICD_REGS_GICD_AFFINITY1_41_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_41_LEN    8
#define GICD_REGS_GICD_AFFINITY0_41_OFFSET 0

#define GICD_REGS_GICD_IRM_42_LEN          1
#define GICD_REGS_GICD_IRM_42_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_42_LEN    8
#define GICD_REGS_GICD_AFFINITY2_42_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_42_LEN    8
#define GICD_REGS_GICD_AFFINITY1_42_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_42_LEN    8
#define GICD_REGS_GICD_AFFINITY0_42_OFFSET 0

#define GICD_REGS_GICD_IRM_43_LEN          1
#define GICD_REGS_GICD_IRM_43_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_43_LEN    8
#define GICD_REGS_GICD_AFFINITY2_43_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_43_LEN    8
#define GICD_REGS_GICD_AFFINITY1_43_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_43_LEN    8
#define GICD_REGS_GICD_AFFINITY0_43_OFFSET 0

#define GICD_REGS_GICD_IRM_44_LEN          1
#define GICD_REGS_GICD_IRM_44_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_44_LEN    8
#define GICD_REGS_GICD_AFFINITY2_44_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_44_LEN    8
#define GICD_REGS_GICD_AFFINITY1_44_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_44_LEN    8
#define GICD_REGS_GICD_AFFINITY0_44_OFFSET 0

#define GICD_REGS_GICD_IRM_45_LEN          1
#define GICD_REGS_GICD_IRM_45_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_45_LEN    8
#define GICD_REGS_GICD_AFFINITY2_45_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_45_LEN    8
#define GICD_REGS_GICD_AFFINITY1_45_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_45_LEN    8
#define GICD_REGS_GICD_AFFINITY0_45_OFFSET 0

#define GICD_REGS_GICD_IRM_46_LEN          1
#define GICD_REGS_GICD_IRM_46_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_46_LEN    8
#define GICD_REGS_GICD_AFFINITY2_46_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_46_LEN    8
#define GICD_REGS_GICD_AFFINITY1_46_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_46_LEN    8
#define GICD_REGS_GICD_AFFINITY0_46_OFFSET 0

#define GICD_REGS_GICD_IRM_47_LEN          1
#define GICD_REGS_GICD_IRM_47_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_47_LEN    8
#define GICD_REGS_GICD_AFFINITY2_47_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_47_LEN    8
#define GICD_REGS_GICD_AFFINITY1_47_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_47_LEN    8
#define GICD_REGS_GICD_AFFINITY0_47_OFFSET 0

#define GICD_REGS_GICD_IRM_48_LEN          1
#define GICD_REGS_GICD_IRM_48_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_48_LEN    8
#define GICD_REGS_GICD_AFFINITY2_48_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_48_LEN    8
#define GICD_REGS_GICD_AFFINITY1_48_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_48_LEN    8
#define GICD_REGS_GICD_AFFINITY0_48_OFFSET 0

#define GICD_REGS_GICD_IRM_49_LEN          1
#define GICD_REGS_GICD_IRM_49_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_49_LEN    8
#define GICD_REGS_GICD_AFFINITY2_49_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_49_LEN    8
#define GICD_REGS_GICD_AFFINITY1_49_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_49_LEN    8
#define GICD_REGS_GICD_AFFINITY0_49_OFFSET 0

#define GICD_REGS_GICD_IRM_50_LEN          1
#define GICD_REGS_GICD_IRM_50_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_50_LEN    8
#define GICD_REGS_GICD_AFFINITY2_50_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_50_LEN    8
#define GICD_REGS_GICD_AFFINITY1_50_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_50_LEN    8
#define GICD_REGS_GICD_AFFINITY0_50_OFFSET 0

#define GICD_REGS_GICD_IRM_51_LEN          1
#define GICD_REGS_GICD_IRM_51_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_51_LEN    8
#define GICD_REGS_GICD_AFFINITY2_51_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_51_LEN    8
#define GICD_REGS_GICD_AFFINITY1_51_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_51_LEN    8
#define GICD_REGS_GICD_AFFINITY0_51_OFFSET 0

#define GICD_REGS_GICD_IRM_52_LEN          1
#define GICD_REGS_GICD_IRM_52_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_52_LEN    8
#define GICD_REGS_GICD_AFFINITY2_52_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_52_LEN    8
#define GICD_REGS_GICD_AFFINITY1_52_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_52_LEN    8
#define GICD_REGS_GICD_AFFINITY0_52_OFFSET 0

#define GICD_REGS_GICD_IRM_53_LEN          1
#define GICD_REGS_GICD_IRM_53_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_53_LEN    8
#define GICD_REGS_GICD_AFFINITY2_53_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_53_LEN    8
#define GICD_REGS_GICD_AFFINITY1_53_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_53_LEN    8
#define GICD_REGS_GICD_AFFINITY0_53_OFFSET 0

#define GICD_REGS_GICD_IRM_54_LEN          1
#define GICD_REGS_GICD_IRM_54_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_54_LEN    8
#define GICD_REGS_GICD_AFFINITY2_54_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_54_LEN    8
#define GICD_REGS_GICD_AFFINITY1_54_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_54_LEN    8
#define GICD_REGS_GICD_AFFINITY0_54_OFFSET 0

#define GICD_REGS_GICD_IRM_55_LEN          1
#define GICD_REGS_GICD_IRM_55_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_55_LEN    8
#define GICD_REGS_GICD_AFFINITY2_55_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_55_LEN    8
#define GICD_REGS_GICD_AFFINITY1_55_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_55_LEN    8
#define GICD_REGS_GICD_AFFINITY0_55_OFFSET 0

#define GICD_REGS_GICD_IRM_56_LEN          1
#define GICD_REGS_GICD_IRM_56_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_56_LEN    8
#define GICD_REGS_GICD_AFFINITY2_56_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_56_LEN    8
#define GICD_REGS_GICD_AFFINITY1_56_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_56_LEN    8
#define GICD_REGS_GICD_AFFINITY0_56_OFFSET 0

#define GICD_REGS_GICD_IRM_57_LEN          1
#define GICD_REGS_GICD_IRM_57_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_57_LEN    8
#define GICD_REGS_GICD_AFFINITY2_57_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_57_LEN    8
#define GICD_REGS_GICD_AFFINITY1_57_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_57_LEN    8
#define GICD_REGS_GICD_AFFINITY0_57_OFFSET 0

#define GICD_REGS_GICD_IRM_58_LEN          1
#define GICD_REGS_GICD_IRM_58_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_58_LEN    8
#define GICD_REGS_GICD_AFFINITY2_58_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_58_LEN    8
#define GICD_REGS_GICD_AFFINITY1_58_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_58_LEN    8
#define GICD_REGS_GICD_AFFINITY0_58_OFFSET 0

#define GICD_REGS_GICD_IRM_59_LEN          1
#define GICD_REGS_GICD_IRM_59_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_59_LEN    8
#define GICD_REGS_GICD_AFFINITY2_59_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_59_LEN    8
#define GICD_REGS_GICD_AFFINITY1_59_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_59_LEN    8
#define GICD_REGS_GICD_AFFINITY0_59_OFFSET 0

#define GICD_REGS_GICD_IRM_60_LEN          1
#define GICD_REGS_GICD_IRM_60_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_60_LEN    8
#define GICD_REGS_GICD_AFFINITY2_60_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_60_LEN    8
#define GICD_REGS_GICD_AFFINITY1_60_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_60_LEN    8
#define GICD_REGS_GICD_AFFINITY0_60_OFFSET 0

#define GICD_REGS_GICD_IRM_61_LEN          1
#define GICD_REGS_GICD_IRM_61_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_61_LEN    8
#define GICD_REGS_GICD_AFFINITY2_61_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_61_LEN    8
#define GICD_REGS_GICD_AFFINITY1_61_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_61_LEN    8
#define GICD_REGS_GICD_AFFINITY0_61_OFFSET 0

#define GICD_REGS_GICD_IRM_62_LEN          1
#define GICD_REGS_GICD_IRM_62_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_62_LEN    8
#define GICD_REGS_GICD_AFFINITY2_62_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_62_LEN    8
#define GICD_REGS_GICD_AFFINITY1_62_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_62_LEN    8
#define GICD_REGS_GICD_AFFINITY0_62_OFFSET 0

#define GICD_REGS_GICD_IRM_63_LEN          1
#define GICD_REGS_GICD_IRM_63_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_63_LEN    8
#define GICD_REGS_GICD_AFFINITY2_63_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_63_LEN    8
#define GICD_REGS_GICD_AFFINITY1_63_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_63_LEN    8
#define GICD_REGS_GICD_AFFINITY0_63_OFFSET 0

#define GICD_REGS_GICD_IRM_64_LEN          1
#define GICD_REGS_GICD_IRM_64_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_64_LEN    8
#define GICD_REGS_GICD_AFFINITY2_64_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_64_LEN    8
#define GICD_REGS_GICD_AFFINITY1_64_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_64_LEN    8
#define GICD_REGS_GICD_AFFINITY0_64_OFFSET 0

#define GICD_REGS_GICD_IRM_65_LEN          1
#define GICD_REGS_GICD_IRM_65_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_65_LEN    8
#define GICD_REGS_GICD_AFFINITY2_65_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_65_LEN    8
#define GICD_REGS_GICD_AFFINITY1_65_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_65_LEN    8
#define GICD_REGS_GICD_AFFINITY0_65_OFFSET 0

#define GICD_REGS_GICD_IRM_66_LEN          1
#define GICD_REGS_GICD_IRM_66_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_66_LEN    8
#define GICD_REGS_GICD_AFFINITY2_66_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_66_LEN    8
#define GICD_REGS_GICD_AFFINITY1_66_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_66_LEN    8
#define GICD_REGS_GICD_AFFINITY0_66_OFFSET 0

#define GICD_REGS_GICD_IRM_67_LEN          1
#define GICD_REGS_GICD_IRM_67_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_67_LEN    8
#define GICD_REGS_GICD_AFFINITY2_67_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_67_LEN    8
#define GICD_REGS_GICD_AFFINITY1_67_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_67_LEN    8
#define GICD_REGS_GICD_AFFINITY0_67_OFFSET 0

#define GICD_REGS_GICD_IRM_68_LEN          1
#define GICD_REGS_GICD_IRM_68_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_68_LEN    8
#define GICD_REGS_GICD_AFFINITY2_68_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_68_LEN    8
#define GICD_REGS_GICD_AFFINITY1_68_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_68_LEN    8
#define GICD_REGS_GICD_AFFINITY0_68_OFFSET 0

#define GICD_REGS_GICD_IRM_69_LEN          1
#define GICD_REGS_GICD_IRM_69_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_69_LEN    8
#define GICD_REGS_GICD_AFFINITY2_69_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_69_LEN    8
#define GICD_REGS_GICD_AFFINITY1_69_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_69_LEN    8
#define GICD_REGS_GICD_AFFINITY0_69_OFFSET 0

#define GICD_REGS_GICD_IRM_70_LEN          1
#define GICD_REGS_GICD_IRM_70_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_70_LEN    8
#define GICD_REGS_GICD_AFFINITY2_70_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_70_LEN    8
#define GICD_REGS_GICD_AFFINITY1_70_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_70_LEN    8
#define GICD_REGS_GICD_AFFINITY0_70_OFFSET 0

#define GICD_REGS_GICD_IRM_71_LEN          1
#define GICD_REGS_GICD_IRM_71_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_71_LEN    8
#define GICD_REGS_GICD_AFFINITY2_71_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_71_LEN    8
#define GICD_REGS_GICD_AFFINITY1_71_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_71_LEN    8
#define GICD_REGS_GICD_AFFINITY0_71_OFFSET 0

#define GICD_REGS_GICD_IRM_72_LEN          1
#define GICD_REGS_GICD_IRM_72_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_72_LEN    8
#define GICD_REGS_GICD_AFFINITY2_72_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_72_LEN    8
#define GICD_REGS_GICD_AFFINITY1_72_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_72_LEN    8
#define GICD_REGS_GICD_AFFINITY0_72_OFFSET 0

#define GICD_REGS_GICD_IRM_73_LEN          1
#define GICD_REGS_GICD_IRM_73_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_73_LEN    8
#define GICD_REGS_GICD_AFFINITY2_73_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_73_LEN    8
#define GICD_REGS_GICD_AFFINITY1_73_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_73_LEN    8
#define GICD_REGS_GICD_AFFINITY0_73_OFFSET 0

#define GICD_REGS_GICD_IRM_74_LEN          1
#define GICD_REGS_GICD_IRM_74_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_74_LEN    8
#define GICD_REGS_GICD_AFFINITY2_74_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_74_LEN    8
#define GICD_REGS_GICD_AFFINITY1_74_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_74_LEN    8
#define GICD_REGS_GICD_AFFINITY0_74_OFFSET 0

#define GICD_REGS_GICD_IRM_75_LEN          1
#define GICD_REGS_GICD_IRM_75_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_75_LEN    8
#define GICD_REGS_GICD_AFFINITY2_75_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_75_LEN    8
#define GICD_REGS_GICD_AFFINITY1_75_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_75_LEN    8
#define GICD_REGS_GICD_AFFINITY0_75_OFFSET 0

#define GICD_REGS_GICD_IRM_76_LEN          1
#define GICD_REGS_GICD_IRM_76_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_76_LEN    8
#define GICD_REGS_GICD_AFFINITY2_76_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_76_LEN    8
#define GICD_REGS_GICD_AFFINITY1_76_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_76_LEN    8
#define GICD_REGS_GICD_AFFINITY0_76_OFFSET 0

#define GICD_REGS_GICD_IRM_77_LEN          1
#define GICD_REGS_GICD_IRM_77_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_77_LEN    8
#define GICD_REGS_GICD_AFFINITY2_77_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_77_LEN    8
#define GICD_REGS_GICD_AFFINITY1_77_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_77_LEN    8
#define GICD_REGS_GICD_AFFINITY0_77_OFFSET 0

#define GICD_REGS_GICD_IRM_78_LEN          1
#define GICD_REGS_GICD_IRM_78_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_78_LEN    8
#define GICD_REGS_GICD_AFFINITY2_78_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_78_LEN    8
#define GICD_REGS_GICD_AFFINITY1_78_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_78_LEN    8
#define GICD_REGS_GICD_AFFINITY0_78_OFFSET 0

#define GICD_REGS_GICD_IRM_79_LEN          1
#define GICD_REGS_GICD_IRM_79_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_79_LEN    8
#define GICD_REGS_GICD_AFFINITY2_79_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_79_LEN    8
#define GICD_REGS_GICD_AFFINITY1_79_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_79_LEN    8
#define GICD_REGS_GICD_AFFINITY0_79_OFFSET 0

#define GICD_REGS_GICD_IRM_80_LEN          1
#define GICD_REGS_GICD_IRM_80_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_80_LEN    8
#define GICD_REGS_GICD_AFFINITY2_80_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_80_LEN    8
#define GICD_REGS_GICD_AFFINITY1_80_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_80_LEN    8
#define GICD_REGS_GICD_AFFINITY0_80_OFFSET 0

#define GICD_REGS_GICD_IRM_81_LEN          1
#define GICD_REGS_GICD_IRM_81_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_81_LEN    8
#define GICD_REGS_GICD_AFFINITY2_81_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_81_LEN    8
#define GICD_REGS_GICD_AFFINITY1_81_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_81_LEN    8
#define GICD_REGS_GICD_AFFINITY0_81_OFFSET 0

#define GICD_REGS_GICD_IRM_82_LEN          1
#define GICD_REGS_GICD_IRM_82_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_82_LEN    8
#define GICD_REGS_GICD_AFFINITY2_82_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_82_LEN    8
#define GICD_REGS_GICD_AFFINITY1_82_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_82_LEN    8
#define GICD_REGS_GICD_AFFINITY0_82_OFFSET 0

#define GICD_REGS_GICD_IRM_83_LEN          1
#define GICD_REGS_GICD_IRM_83_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_83_LEN    8
#define GICD_REGS_GICD_AFFINITY2_83_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_83_LEN    8
#define GICD_REGS_GICD_AFFINITY1_83_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_83_LEN    8
#define GICD_REGS_GICD_AFFINITY0_83_OFFSET 0

#define GICD_REGS_GICD_IRM_84_LEN          1
#define GICD_REGS_GICD_IRM_84_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_84_LEN    8
#define GICD_REGS_GICD_AFFINITY2_84_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_84_LEN    8
#define GICD_REGS_GICD_AFFINITY1_84_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_84_LEN    8
#define GICD_REGS_GICD_AFFINITY0_84_OFFSET 0

#define GICD_REGS_GICD_IRM_85_LEN          1
#define GICD_REGS_GICD_IRM_85_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_85_LEN    8
#define GICD_REGS_GICD_AFFINITY2_85_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_85_LEN    8
#define GICD_REGS_GICD_AFFINITY1_85_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_85_LEN    8
#define GICD_REGS_GICD_AFFINITY0_85_OFFSET 0

#define GICD_REGS_GICD_IRM_86_LEN          1
#define GICD_REGS_GICD_IRM_86_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_86_LEN    8
#define GICD_REGS_GICD_AFFINITY2_86_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_86_LEN    8
#define GICD_REGS_GICD_AFFINITY1_86_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_86_LEN    8
#define GICD_REGS_GICD_AFFINITY0_86_OFFSET 0

#define GICD_REGS_GICD_IRM_87_LEN          1
#define GICD_REGS_GICD_IRM_87_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_87_LEN    8
#define GICD_REGS_GICD_AFFINITY2_87_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_87_LEN    8
#define GICD_REGS_GICD_AFFINITY1_87_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_87_LEN    8
#define GICD_REGS_GICD_AFFINITY0_87_OFFSET 0

#define GICD_REGS_GICD_IRM_88_LEN          1
#define GICD_REGS_GICD_IRM_88_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_88_LEN    8
#define GICD_REGS_GICD_AFFINITY2_88_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_88_LEN    8
#define GICD_REGS_GICD_AFFINITY1_88_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_88_LEN    8
#define GICD_REGS_GICD_AFFINITY0_88_OFFSET 0

#define GICD_REGS_GICD_IRM_89_LEN          1
#define GICD_REGS_GICD_IRM_89_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_89_LEN    8
#define GICD_REGS_GICD_AFFINITY2_89_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_89_LEN    8
#define GICD_REGS_GICD_AFFINITY1_89_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_89_LEN    8
#define GICD_REGS_GICD_AFFINITY0_89_OFFSET 0

#define GICD_REGS_GICD_IRM_90_LEN          1
#define GICD_REGS_GICD_IRM_90_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_90_LEN    8
#define GICD_REGS_GICD_AFFINITY2_90_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_90_LEN    8
#define GICD_REGS_GICD_AFFINITY1_90_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_90_LEN    8
#define GICD_REGS_GICD_AFFINITY0_90_OFFSET 0

#define GICD_REGS_GICD_IRM_91_LEN          1
#define GICD_REGS_GICD_IRM_91_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_91_LEN    8
#define GICD_REGS_GICD_AFFINITY2_91_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_91_LEN    8
#define GICD_REGS_GICD_AFFINITY1_91_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_91_LEN    8
#define GICD_REGS_GICD_AFFINITY0_91_OFFSET 0

#define GICD_REGS_GICD_IRM_92_LEN          1
#define GICD_REGS_GICD_IRM_92_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_92_LEN    8
#define GICD_REGS_GICD_AFFINITY2_92_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_92_LEN    8
#define GICD_REGS_GICD_AFFINITY1_92_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_92_LEN    8
#define GICD_REGS_GICD_AFFINITY0_92_OFFSET 0

#define GICD_REGS_GICD_IRM_93_LEN          1
#define GICD_REGS_GICD_IRM_93_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_93_LEN    8
#define GICD_REGS_GICD_AFFINITY2_93_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_93_LEN    8
#define GICD_REGS_GICD_AFFINITY1_93_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_93_LEN    8
#define GICD_REGS_GICD_AFFINITY0_93_OFFSET 0

#define GICD_REGS_GICD_IRM_94_LEN          1
#define GICD_REGS_GICD_IRM_94_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_94_LEN    8
#define GICD_REGS_GICD_AFFINITY2_94_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_94_LEN    8
#define GICD_REGS_GICD_AFFINITY1_94_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_94_LEN    8
#define GICD_REGS_GICD_AFFINITY0_94_OFFSET 0

#define GICD_REGS_GICD_IRM_95_LEN          1
#define GICD_REGS_GICD_IRM_95_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_95_LEN    8
#define GICD_REGS_GICD_AFFINITY2_95_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_95_LEN    8
#define GICD_REGS_GICD_AFFINITY1_95_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_95_LEN    8
#define GICD_REGS_GICD_AFFINITY0_95_OFFSET 0

#define GICD_REGS_GICD_IRM_96_LEN          1
#define GICD_REGS_GICD_IRM_96_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_96_LEN    8
#define GICD_REGS_GICD_AFFINITY2_96_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_96_LEN    8
#define GICD_REGS_GICD_AFFINITY1_96_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_96_LEN    8
#define GICD_REGS_GICD_AFFINITY0_96_OFFSET 0

#define GICD_REGS_GICD_IRM_97_LEN          1
#define GICD_REGS_GICD_IRM_97_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_97_LEN    8
#define GICD_REGS_GICD_AFFINITY2_97_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_97_LEN    8
#define GICD_REGS_GICD_AFFINITY1_97_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_97_LEN    8
#define GICD_REGS_GICD_AFFINITY0_97_OFFSET 0

#define GICD_REGS_GICD_IRM_98_LEN          1
#define GICD_REGS_GICD_IRM_98_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_98_LEN    8
#define GICD_REGS_GICD_AFFINITY2_98_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_98_LEN    8
#define GICD_REGS_GICD_AFFINITY1_98_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_98_LEN    8
#define GICD_REGS_GICD_AFFINITY0_98_OFFSET 0

#define GICD_REGS_GICD_IRM_99_LEN          1
#define GICD_REGS_GICD_IRM_99_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_99_LEN    8
#define GICD_REGS_GICD_AFFINITY2_99_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_99_LEN    8
#define GICD_REGS_GICD_AFFINITY1_99_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_99_LEN    8
#define GICD_REGS_GICD_AFFINITY0_99_OFFSET 0

#define GICD_REGS_GICD_IRM_100_LEN          1
#define GICD_REGS_GICD_IRM_100_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_100_LEN    8
#define GICD_REGS_GICD_AFFINITY2_100_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_100_LEN    8
#define GICD_REGS_GICD_AFFINITY1_100_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_100_LEN    8
#define GICD_REGS_GICD_AFFINITY0_100_OFFSET 0

#define GICD_REGS_GICD_IRM_101_LEN          1
#define GICD_REGS_GICD_IRM_101_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_101_LEN    8
#define GICD_REGS_GICD_AFFINITY2_101_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_101_LEN    8
#define GICD_REGS_GICD_AFFINITY1_101_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_101_LEN    8
#define GICD_REGS_GICD_AFFINITY0_101_OFFSET 0

#define GICD_REGS_GICD_IRM_102_LEN          1
#define GICD_REGS_GICD_IRM_102_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_102_LEN    8
#define GICD_REGS_GICD_AFFINITY2_102_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_102_LEN    8
#define GICD_REGS_GICD_AFFINITY1_102_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_102_LEN    8
#define GICD_REGS_GICD_AFFINITY0_102_OFFSET 0

#define GICD_REGS_GICD_IRM_103_LEN          1
#define GICD_REGS_GICD_IRM_103_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_103_LEN    8
#define GICD_REGS_GICD_AFFINITY2_103_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_103_LEN    8
#define GICD_REGS_GICD_AFFINITY1_103_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_103_LEN    8
#define GICD_REGS_GICD_AFFINITY0_103_OFFSET 0

#define GICD_REGS_GICD_IRM_104_LEN          1
#define GICD_REGS_GICD_IRM_104_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_104_LEN    8
#define GICD_REGS_GICD_AFFINITY2_104_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_104_LEN    8
#define GICD_REGS_GICD_AFFINITY1_104_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_104_LEN    8
#define GICD_REGS_GICD_AFFINITY0_104_OFFSET 0

#define GICD_REGS_GICD_IRM_105_LEN          1
#define GICD_REGS_GICD_IRM_105_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_105_LEN    8
#define GICD_REGS_GICD_AFFINITY2_105_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_105_LEN    8
#define GICD_REGS_GICD_AFFINITY1_105_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_105_LEN    8
#define GICD_REGS_GICD_AFFINITY0_105_OFFSET 0

#define GICD_REGS_GICD_IRM_106_LEN          1
#define GICD_REGS_GICD_IRM_106_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_106_LEN    8
#define GICD_REGS_GICD_AFFINITY2_106_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_106_LEN    8
#define GICD_REGS_GICD_AFFINITY1_106_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_106_LEN    8
#define GICD_REGS_GICD_AFFINITY0_106_OFFSET 0

#define GICD_REGS_GICD_IRM_107_LEN          1
#define GICD_REGS_GICD_IRM_107_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_107_LEN    8
#define GICD_REGS_GICD_AFFINITY2_107_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_107_LEN    8
#define GICD_REGS_GICD_AFFINITY1_107_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_107_LEN    8
#define GICD_REGS_GICD_AFFINITY0_107_OFFSET 0

#define GICD_REGS_GICD_IRM_108_LEN          1
#define GICD_REGS_GICD_IRM_108_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_108_LEN    8
#define GICD_REGS_GICD_AFFINITY2_108_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_108_LEN    8
#define GICD_REGS_GICD_AFFINITY1_108_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_108_LEN    8
#define GICD_REGS_GICD_AFFINITY0_108_OFFSET 0

#define GICD_REGS_GICD_IRM_109_LEN          1
#define GICD_REGS_GICD_IRM_109_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_109_LEN    8
#define GICD_REGS_GICD_AFFINITY2_109_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_109_LEN    8
#define GICD_REGS_GICD_AFFINITY1_109_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_109_LEN    8
#define GICD_REGS_GICD_AFFINITY0_109_OFFSET 0

#define GICD_REGS_GICD_IRM_110_LEN          1
#define GICD_REGS_GICD_IRM_110_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_110_LEN    8
#define GICD_REGS_GICD_AFFINITY2_110_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_110_LEN    8
#define GICD_REGS_GICD_AFFINITY1_110_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_110_LEN    8
#define GICD_REGS_GICD_AFFINITY0_110_OFFSET 0

#define GICD_REGS_GICD_IRM_111_LEN          1
#define GICD_REGS_GICD_IRM_111_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_111_LEN    8
#define GICD_REGS_GICD_AFFINITY2_111_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_111_LEN    8
#define GICD_REGS_GICD_AFFINITY1_111_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_111_LEN    8
#define GICD_REGS_GICD_AFFINITY0_111_OFFSET 0

#define GICD_REGS_GICD_IRM_112_LEN          1
#define GICD_REGS_GICD_IRM_112_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_112_LEN    8
#define GICD_REGS_GICD_AFFINITY2_112_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_112_LEN    8
#define GICD_REGS_GICD_AFFINITY1_112_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_112_LEN    8
#define GICD_REGS_GICD_AFFINITY0_112_OFFSET 0

#define GICD_REGS_GICD_IRM_113_LEN          1
#define GICD_REGS_GICD_IRM_113_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_113_LEN    8
#define GICD_REGS_GICD_AFFINITY2_113_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_113_LEN    8
#define GICD_REGS_GICD_AFFINITY1_113_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_113_LEN    8
#define GICD_REGS_GICD_AFFINITY0_113_OFFSET 0

#define GICD_REGS_GICD_IRM_114_LEN          1
#define GICD_REGS_GICD_IRM_114_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_114_LEN    8
#define GICD_REGS_GICD_AFFINITY2_114_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_114_LEN    8
#define GICD_REGS_GICD_AFFINITY1_114_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_114_LEN    8
#define GICD_REGS_GICD_AFFINITY0_114_OFFSET 0

#define GICD_REGS_GICD_IRM_115_LEN          1
#define GICD_REGS_GICD_IRM_115_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_115_LEN    8
#define GICD_REGS_GICD_AFFINITY2_115_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_115_LEN    8
#define GICD_REGS_GICD_AFFINITY1_115_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_115_LEN    8
#define GICD_REGS_GICD_AFFINITY0_115_OFFSET 0

#define GICD_REGS_GICD_IRM_116_LEN          1
#define GICD_REGS_GICD_IRM_116_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_116_LEN    8
#define GICD_REGS_GICD_AFFINITY2_116_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_116_LEN    8
#define GICD_REGS_GICD_AFFINITY1_116_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_116_LEN    8
#define GICD_REGS_GICD_AFFINITY0_116_OFFSET 0

#define GICD_REGS_GICD_IRM_117_LEN          1
#define GICD_REGS_GICD_IRM_117_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_117_LEN    8
#define GICD_REGS_GICD_AFFINITY2_117_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_117_LEN    8
#define GICD_REGS_GICD_AFFINITY1_117_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_117_LEN    8
#define GICD_REGS_GICD_AFFINITY0_117_OFFSET 0

#define GICD_REGS_GICD_IRM_118_LEN          1
#define GICD_REGS_GICD_IRM_118_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_118_LEN    8
#define GICD_REGS_GICD_AFFINITY2_118_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_118_LEN    8
#define GICD_REGS_GICD_AFFINITY1_118_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_118_LEN    8
#define GICD_REGS_GICD_AFFINITY0_118_OFFSET 0

#define GICD_REGS_GICD_IRM_119_LEN          1
#define GICD_REGS_GICD_IRM_119_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_119_LEN    8
#define GICD_REGS_GICD_AFFINITY2_119_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_119_LEN    8
#define GICD_REGS_GICD_AFFINITY1_119_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_119_LEN    8
#define GICD_REGS_GICD_AFFINITY0_119_OFFSET 0

#define GICD_REGS_GICD_IRM_120_LEN          1
#define GICD_REGS_GICD_IRM_120_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_120_LEN    8
#define GICD_REGS_GICD_AFFINITY2_120_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_120_LEN    8
#define GICD_REGS_GICD_AFFINITY1_120_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_120_LEN    8
#define GICD_REGS_GICD_AFFINITY0_120_OFFSET 0

#define GICD_REGS_GICD_IRM_121_LEN          1
#define GICD_REGS_GICD_IRM_121_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_121_LEN    8
#define GICD_REGS_GICD_AFFINITY2_121_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_121_LEN    8
#define GICD_REGS_GICD_AFFINITY1_121_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_121_LEN    8
#define GICD_REGS_GICD_AFFINITY0_121_OFFSET 0

#define GICD_REGS_GICD_IRM_122_LEN          1
#define GICD_REGS_GICD_IRM_122_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_122_LEN    8
#define GICD_REGS_GICD_AFFINITY2_122_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_122_LEN    8
#define GICD_REGS_GICD_AFFINITY1_122_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_122_LEN    8
#define GICD_REGS_GICD_AFFINITY0_122_OFFSET 0

#define GICD_REGS_GICD_IRM_123_LEN          1
#define GICD_REGS_GICD_IRM_123_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_123_LEN    8
#define GICD_REGS_GICD_AFFINITY2_123_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_123_LEN    8
#define GICD_REGS_GICD_AFFINITY1_123_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_123_LEN    8
#define GICD_REGS_GICD_AFFINITY0_123_OFFSET 0

#define GICD_REGS_GICD_IRM_124_LEN          1
#define GICD_REGS_GICD_IRM_124_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_124_LEN    8
#define GICD_REGS_GICD_AFFINITY2_124_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_124_LEN    8
#define GICD_REGS_GICD_AFFINITY1_124_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_124_LEN    8
#define GICD_REGS_GICD_AFFINITY0_124_OFFSET 0

#define GICD_REGS_GICD_IRM_125_LEN          1
#define GICD_REGS_GICD_IRM_125_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_125_LEN    8
#define GICD_REGS_GICD_AFFINITY2_125_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_125_LEN    8
#define GICD_REGS_GICD_AFFINITY1_125_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_125_LEN    8
#define GICD_REGS_GICD_AFFINITY0_125_OFFSET 0

#define GICD_REGS_GICD_IRM_126_LEN          1
#define GICD_REGS_GICD_IRM_126_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_126_LEN    8
#define GICD_REGS_GICD_AFFINITY2_126_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_126_LEN    8
#define GICD_REGS_GICD_AFFINITY1_126_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_126_LEN    8
#define GICD_REGS_GICD_AFFINITY0_126_OFFSET 0

#define GICD_REGS_GICD_IRM_127_LEN          1
#define GICD_REGS_GICD_IRM_127_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_127_LEN    8
#define GICD_REGS_GICD_AFFINITY2_127_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_127_LEN    8
#define GICD_REGS_GICD_AFFINITY1_127_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_127_LEN    8
#define GICD_REGS_GICD_AFFINITY0_127_OFFSET 0

#define GICD_REGS_GICD_IRM_128_LEN          1
#define GICD_REGS_GICD_IRM_128_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_128_LEN    8
#define GICD_REGS_GICD_AFFINITY2_128_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_128_LEN    8
#define GICD_REGS_GICD_AFFINITY1_128_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_128_LEN    8
#define GICD_REGS_GICD_AFFINITY0_128_OFFSET 0

#define GICD_REGS_GICD_IRM_129_LEN          1
#define GICD_REGS_GICD_IRM_129_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_129_LEN    8
#define GICD_REGS_GICD_AFFINITY2_129_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_129_LEN    8
#define GICD_REGS_GICD_AFFINITY1_129_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_129_LEN    8
#define GICD_REGS_GICD_AFFINITY0_129_OFFSET 0

#define GICD_REGS_GICD_IRM_130_LEN          1
#define GICD_REGS_GICD_IRM_130_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_130_LEN    8
#define GICD_REGS_GICD_AFFINITY2_130_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_130_LEN    8
#define GICD_REGS_GICD_AFFINITY1_130_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_130_LEN    8
#define GICD_REGS_GICD_AFFINITY0_130_OFFSET 0

#define GICD_REGS_GICD_IRM_131_LEN          1
#define GICD_REGS_GICD_IRM_131_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_131_LEN    8
#define GICD_REGS_GICD_AFFINITY2_131_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_131_LEN    8
#define GICD_REGS_GICD_AFFINITY1_131_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_131_LEN    8
#define GICD_REGS_GICD_AFFINITY0_131_OFFSET 0

#define GICD_REGS_GICD_IRM_132_LEN          1
#define GICD_REGS_GICD_IRM_132_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_132_LEN    8
#define GICD_REGS_GICD_AFFINITY2_132_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_132_LEN    8
#define GICD_REGS_GICD_AFFINITY1_132_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_132_LEN    8
#define GICD_REGS_GICD_AFFINITY0_132_OFFSET 0

#define GICD_REGS_GICD_IRM_133_LEN          1
#define GICD_REGS_GICD_IRM_133_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_133_LEN    8
#define GICD_REGS_GICD_AFFINITY2_133_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_133_LEN    8
#define GICD_REGS_GICD_AFFINITY1_133_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_133_LEN    8
#define GICD_REGS_GICD_AFFINITY0_133_OFFSET 0

#define GICD_REGS_GICD_IRM_134_LEN          1
#define GICD_REGS_GICD_IRM_134_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_134_LEN    8
#define GICD_REGS_GICD_AFFINITY2_134_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_134_LEN    8
#define GICD_REGS_GICD_AFFINITY1_134_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_134_LEN    8
#define GICD_REGS_GICD_AFFINITY0_134_OFFSET 0

#define GICD_REGS_GICD_IRM_135_LEN          1
#define GICD_REGS_GICD_IRM_135_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_135_LEN    8
#define GICD_REGS_GICD_AFFINITY2_135_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_135_LEN    8
#define GICD_REGS_GICD_AFFINITY1_135_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_135_LEN    8
#define GICD_REGS_GICD_AFFINITY0_135_OFFSET 0

#define GICD_REGS_GICD_IRM_136_LEN          1
#define GICD_REGS_GICD_IRM_136_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_136_LEN    8
#define GICD_REGS_GICD_AFFINITY2_136_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_136_LEN    8
#define GICD_REGS_GICD_AFFINITY1_136_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_136_LEN    8
#define GICD_REGS_GICD_AFFINITY0_136_OFFSET 0

#define GICD_REGS_GICD_IRM_137_LEN          1
#define GICD_REGS_GICD_IRM_137_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_137_LEN    8
#define GICD_REGS_GICD_AFFINITY2_137_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_137_LEN    8
#define GICD_REGS_GICD_AFFINITY1_137_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_137_LEN    8
#define GICD_REGS_GICD_AFFINITY0_137_OFFSET 0

#define GICD_REGS_GICD_IRM_138_LEN          1
#define GICD_REGS_GICD_IRM_138_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_138_LEN    8
#define GICD_REGS_GICD_AFFINITY2_138_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_138_LEN    8
#define GICD_REGS_GICD_AFFINITY1_138_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_138_LEN    8
#define GICD_REGS_GICD_AFFINITY0_138_OFFSET 0

#define GICD_REGS_GICD_IRM_139_LEN          1
#define GICD_REGS_GICD_IRM_139_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_139_LEN    8
#define GICD_REGS_GICD_AFFINITY2_139_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_139_LEN    8
#define GICD_REGS_GICD_AFFINITY1_139_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_139_LEN    8
#define GICD_REGS_GICD_AFFINITY0_139_OFFSET 0

#define GICD_REGS_GICD_IRM_140_LEN          1
#define GICD_REGS_GICD_IRM_140_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_140_LEN    8
#define GICD_REGS_GICD_AFFINITY2_140_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_140_LEN    8
#define GICD_REGS_GICD_AFFINITY1_140_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_140_LEN    8
#define GICD_REGS_GICD_AFFINITY0_140_OFFSET 0

#define GICD_REGS_GICD_IRM_141_LEN          1
#define GICD_REGS_GICD_IRM_141_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_141_LEN    8
#define GICD_REGS_GICD_AFFINITY2_141_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_141_LEN    8
#define GICD_REGS_GICD_AFFINITY1_141_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_141_LEN    8
#define GICD_REGS_GICD_AFFINITY0_141_OFFSET 0

#define GICD_REGS_GICD_IRM_142_LEN          1
#define GICD_REGS_GICD_IRM_142_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_142_LEN    8
#define GICD_REGS_GICD_AFFINITY2_142_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_142_LEN    8
#define GICD_REGS_GICD_AFFINITY1_142_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_142_LEN    8
#define GICD_REGS_GICD_AFFINITY0_142_OFFSET 0

#define GICD_REGS_GICD_IRM_143_LEN          1
#define GICD_REGS_GICD_IRM_143_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_143_LEN    8
#define GICD_REGS_GICD_AFFINITY2_143_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_143_LEN    8
#define GICD_REGS_GICD_AFFINITY1_143_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_143_LEN    8
#define GICD_REGS_GICD_AFFINITY0_143_OFFSET 0

#define GICD_REGS_GICD_IRM_144_LEN          1
#define GICD_REGS_GICD_IRM_144_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_144_LEN    8
#define GICD_REGS_GICD_AFFINITY2_144_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_144_LEN    8
#define GICD_REGS_GICD_AFFINITY1_144_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_144_LEN    8
#define GICD_REGS_GICD_AFFINITY0_144_OFFSET 0

#define GICD_REGS_GICD_IRM_145_LEN          1
#define GICD_REGS_GICD_IRM_145_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_145_LEN    8
#define GICD_REGS_GICD_AFFINITY2_145_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_145_LEN    8
#define GICD_REGS_GICD_AFFINITY1_145_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_145_LEN    8
#define GICD_REGS_GICD_AFFINITY0_145_OFFSET 0

#define GICD_REGS_GICD_IRM_146_LEN          1
#define GICD_REGS_GICD_IRM_146_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_146_LEN    8
#define GICD_REGS_GICD_AFFINITY2_146_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_146_LEN    8
#define GICD_REGS_GICD_AFFINITY1_146_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_146_LEN    8
#define GICD_REGS_GICD_AFFINITY0_146_OFFSET 0

#define GICD_REGS_GICD_IRM_147_LEN          1
#define GICD_REGS_GICD_IRM_147_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_147_LEN    8
#define GICD_REGS_GICD_AFFINITY2_147_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_147_LEN    8
#define GICD_REGS_GICD_AFFINITY1_147_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_147_LEN    8
#define GICD_REGS_GICD_AFFINITY0_147_OFFSET 0

#define GICD_REGS_GICD_IRM_148_LEN          1
#define GICD_REGS_GICD_IRM_148_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_148_LEN    8
#define GICD_REGS_GICD_AFFINITY2_148_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_148_LEN    8
#define GICD_REGS_GICD_AFFINITY1_148_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_148_LEN    8
#define GICD_REGS_GICD_AFFINITY0_148_OFFSET 0

#define GICD_REGS_GICD_IRM_149_LEN          1
#define GICD_REGS_GICD_IRM_149_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_149_LEN    8
#define GICD_REGS_GICD_AFFINITY2_149_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_149_LEN    8
#define GICD_REGS_GICD_AFFINITY1_149_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_149_LEN    8
#define GICD_REGS_GICD_AFFINITY0_149_OFFSET 0

#define GICD_REGS_GICD_IRM_150_LEN          1
#define GICD_REGS_GICD_IRM_150_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_150_LEN    8
#define GICD_REGS_GICD_AFFINITY2_150_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_150_LEN    8
#define GICD_REGS_GICD_AFFINITY1_150_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_150_LEN    8
#define GICD_REGS_GICD_AFFINITY0_150_OFFSET 0

#define GICD_REGS_GICD_IRM_151_LEN          1
#define GICD_REGS_GICD_IRM_151_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_151_LEN    8
#define GICD_REGS_GICD_AFFINITY2_151_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_151_LEN    8
#define GICD_REGS_GICD_AFFINITY1_151_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_151_LEN    8
#define GICD_REGS_GICD_AFFINITY0_151_OFFSET 0

#define GICD_REGS_GICD_IRM_152_LEN          1
#define GICD_REGS_GICD_IRM_152_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_152_LEN    8
#define GICD_REGS_GICD_AFFINITY2_152_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_152_LEN    8
#define GICD_REGS_GICD_AFFINITY1_152_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_152_LEN    8
#define GICD_REGS_GICD_AFFINITY0_152_OFFSET 0

#define GICD_REGS_GICD_IRM_153_LEN          1
#define GICD_REGS_GICD_IRM_153_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_153_LEN    8
#define GICD_REGS_GICD_AFFINITY2_153_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_153_LEN    8
#define GICD_REGS_GICD_AFFINITY1_153_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_153_LEN    8
#define GICD_REGS_GICD_AFFINITY0_153_OFFSET 0

#define GICD_REGS_GICD_IRM_154_LEN          1
#define GICD_REGS_GICD_IRM_154_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_154_LEN    8
#define GICD_REGS_GICD_AFFINITY2_154_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_154_LEN    8
#define GICD_REGS_GICD_AFFINITY1_154_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_154_LEN    8
#define GICD_REGS_GICD_AFFINITY0_154_OFFSET 0

#define GICD_REGS_GICD_IRM_155_LEN          1
#define GICD_REGS_GICD_IRM_155_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_155_LEN    8
#define GICD_REGS_GICD_AFFINITY2_155_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_155_LEN    8
#define GICD_REGS_GICD_AFFINITY1_155_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_155_LEN    8
#define GICD_REGS_GICD_AFFINITY0_155_OFFSET 0

#define GICD_REGS_GICD_IRM_156_LEN          1
#define GICD_REGS_GICD_IRM_156_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_156_LEN    8
#define GICD_REGS_GICD_AFFINITY2_156_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_156_LEN    8
#define GICD_REGS_GICD_AFFINITY1_156_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_156_LEN    8
#define GICD_REGS_GICD_AFFINITY0_156_OFFSET 0

#define GICD_REGS_GICD_IRM_157_LEN          1
#define GICD_REGS_GICD_IRM_157_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_157_LEN    8
#define GICD_REGS_GICD_AFFINITY2_157_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_157_LEN    8
#define GICD_REGS_GICD_AFFINITY1_157_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_157_LEN    8
#define GICD_REGS_GICD_AFFINITY0_157_OFFSET 0

#define GICD_REGS_GICD_IRM_158_LEN          1
#define GICD_REGS_GICD_IRM_158_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_158_LEN    8
#define GICD_REGS_GICD_AFFINITY2_158_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_158_LEN    8
#define GICD_REGS_GICD_AFFINITY1_158_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_158_LEN    8
#define GICD_REGS_GICD_AFFINITY0_158_OFFSET 0

#define GICD_REGS_GICD_IRM_159_LEN          1
#define GICD_REGS_GICD_IRM_159_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_159_LEN    8
#define GICD_REGS_GICD_AFFINITY2_159_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_159_LEN    8
#define GICD_REGS_GICD_AFFINITY1_159_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_159_LEN    8
#define GICD_REGS_GICD_AFFINITY0_159_OFFSET 0

#define GICD_REGS_GICD_IRM_160_LEN          1
#define GICD_REGS_GICD_IRM_160_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_160_LEN    8
#define GICD_REGS_GICD_AFFINITY2_160_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_160_LEN    8
#define GICD_REGS_GICD_AFFINITY1_160_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_160_LEN    8
#define GICD_REGS_GICD_AFFINITY0_160_OFFSET 0

#define GICD_REGS_GICD_IRM_161_LEN          1
#define GICD_REGS_GICD_IRM_161_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_161_LEN    8
#define GICD_REGS_GICD_AFFINITY2_161_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_161_LEN    8
#define GICD_REGS_GICD_AFFINITY1_161_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_161_LEN    8
#define GICD_REGS_GICD_AFFINITY0_161_OFFSET 0

#define GICD_REGS_GICD_IRM_162_LEN          1
#define GICD_REGS_GICD_IRM_162_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_162_LEN    8
#define GICD_REGS_GICD_AFFINITY2_162_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_162_LEN    8
#define GICD_REGS_GICD_AFFINITY1_162_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_162_LEN    8
#define GICD_REGS_GICD_AFFINITY0_162_OFFSET 0

#define GICD_REGS_GICD_IRM_163_LEN          1
#define GICD_REGS_GICD_IRM_163_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_163_LEN    8
#define GICD_REGS_GICD_AFFINITY2_163_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_163_LEN    8
#define GICD_REGS_GICD_AFFINITY1_163_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_163_LEN    8
#define GICD_REGS_GICD_AFFINITY0_163_OFFSET 0

#define GICD_REGS_GICD_IRM_164_LEN          1
#define GICD_REGS_GICD_IRM_164_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_164_LEN    8
#define GICD_REGS_GICD_AFFINITY2_164_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_164_LEN    8
#define GICD_REGS_GICD_AFFINITY1_164_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_164_LEN    8
#define GICD_REGS_GICD_AFFINITY0_164_OFFSET 0

#define GICD_REGS_GICD_IRM_165_LEN          1
#define GICD_REGS_GICD_IRM_165_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_165_LEN    8
#define GICD_REGS_GICD_AFFINITY2_165_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_165_LEN    8
#define GICD_REGS_GICD_AFFINITY1_165_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_165_LEN    8
#define GICD_REGS_GICD_AFFINITY0_165_OFFSET 0

#define GICD_REGS_GICD_IRM_166_LEN          1
#define GICD_REGS_GICD_IRM_166_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_166_LEN    8
#define GICD_REGS_GICD_AFFINITY2_166_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_166_LEN    8
#define GICD_REGS_GICD_AFFINITY1_166_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_166_LEN    8
#define GICD_REGS_GICD_AFFINITY0_166_OFFSET 0

#define GICD_REGS_GICD_IRM_167_LEN          1
#define GICD_REGS_GICD_IRM_167_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_167_LEN    8
#define GICD_REGS_GICD_AFFINITY2_167_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_167_LEN    8
#define GICD_REGS_GICD_AFFINITY1_167_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_167_LEN    8
#define GICD_REGS_GICD_AFFINITY0_167_OFFSET 0

#define GICD_REGS_GICD_IRM_168_LEN          1
#define GICD_REGS_GICD_IRM_168_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_168_LEN    8
#define GICD_REGS_GICD_AFFINITY2_168_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_168_LEN    8
#define GICD_REGS_GICD_AFFINITY1_168_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_168_LEN    8
#define GICD_REGS_GICD_AFFINITY0_168_OFFSET 0

#define GICD_REGS_GICD_IRM_169_LEN          1
#define GICD_REGS_GICD_IRM_169_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_169_LEN    8
#define GICD_REGS_GICD_AFFINITY2_169_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_169_LEN    8
#define GICD_REGS_GICD_AFFINITY1_169_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_169_LEN    8
#define GICD_REGS_GICD_AFFINITY0_169_OFFSET 0

#define GICD_REGS_GICD_IRM_170_LEN          1
#define GICD_REGS_GICD_IRM_170_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_170_LEN    8
#define GICD_REGS_GICD_AFFINITY2_170_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_170_LEN    8
#define GICD_REGS_GICD_AFFINITY1_170_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_170_LEN    8
#define GICD_REGS_GICD_AFFINITY0_170_OFFSET 0

#define GICD_REGS_GICD_IRM_171_LEN          1
#define GICD_REGS_GICD_IRM_171_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_171_LEN    8
#define GICD_REGS_GICD_AFFINITY2_171_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_171_LEN    8
#define GICD_REGS_GICD_AFFINITY1_171_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_171_LEN    8
#define GICD_REGS_GICD_AFFINITY0_171_OFFSET 0

#define GICD_REGS_GICD_IRM_172_LEN          1
#define GICD_REGS_GICD_IRM_172_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_172_LEN    8
#define GICD_REGS_GICD_AFFINITY2_172_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_172_LEN    8
#define GICD_REGS_GICD_AFFINITY1_172_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_172_LEN    8
#define GICD_REGS_GICD_AFFINITY0_172_OFFSET 0

#define GICD_REGS_GICD_IRM_173_LEN          1
#define GICD_REGS_GICD_IRM_173_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_173_LEN    8
#define GICD_REGS_GICD_AFFINITY2_173_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_173_LEN    8
#define GICD_REGS_GICD_AFFINITY1_173_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_173_LEN    8
#define GICD_REGS_GICD_AFFINITY0_173_OFFSET 0

#define GICD_REGS_GICD_IRM_174_LEN          1
#define GICD_REGS_GICD_IRM_174_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_174_LEN    8
#define GICD_REGS_GICD_AFFINITY2_174_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_174_LEN    8
#define GICD_REGS_GICD_AFFINITY1_174_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_174_LEN    8
#define GICD_REGS_GICD_AFFINITY0_174_OFFSET 0

#define GICD_REGS_GICD_IRM_175_LEN          1
#define GICD_REGS_GICD_IRM_175_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_175_LEN    8
#define GICD_REGS_GICD_AFFINITY2_175_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_175_LEN    8
#define GICD_REGS_GICD_AFFINITY1_175_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_175_LEN    8
#define GICD_REGS_GICD_AFFINITY0_175_OFFSET 0

#define GICD_REGS_GICD_IRM_176_LEN          1
#define GICD_REGS_GICD_IRM_176_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_176_LEN    8
#define GICD_REGS_GICD_AFFINITY2_176_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_176_LEN    8
#define GICD_REGS_GICD_AFFINITY1_176_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_176_LEN    8
#define GICD_REGS_GICD_AFFINITY0_176_OFFSET 0

#define GICD_REGS_GICD_IRM_177_LEN          1
#define GICD_REGS_GICD_IRM_177_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_177_LEN    8
#define GICD_REGS_GICD_AFFINITY2_177_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_177_LEN    8
#define GICD_REGS_GICD_AFFINITY1_177_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_177_LEN    8
#define GICD_REGS_GICD_AFFINITY0_177_OFFSET 0

#define GICD_REGS_GICD_IRM_178_LEN          1
#define GICD_REGS_GICD_IRM_178_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_178_LEN    8
#define GICD_REGS_GICD_AFFINITY2_178_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_178_LEN    8
#define GICD_REGS_GICD_AFFINITY1_178_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_178_LEN    8
#define GICD_REGS_GICD_AFFINITY0_178_OFFSET 0

#define GICD_REGS_GICD_IRM_179_LEN          1
#define GICD_REGS_GICD_IRM_179_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_179_LEN    8
#define GICD_REGS_GICD_AFFINITY2_179_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_179_LEN    8
#define GICD_REGS_GICD_AFFINITY1_179_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_179_LEN    8
#define GICD_REGS_GICD_AFFINITY0_179_OFFSET 0

#define GICD_REGS_GICD_IRM_180_LEN          1
#define GICD_REGS_GICD_IRM_180_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_180_LEN    8
#define GICD_REGS_GICD_AFFINITY2_180_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_180_LEN    8
#define GICD_REGS_GICD_AFFINITY1_180_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_180_LEN    8
#define GICD_REGS_GICD_AFFINITY0_180_OFFSET 0

#define GICD_REGS_GICD_IRM_181_LEN          1
#define GICD_REGS_GICD_IRM_181_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_181_LEN    8
#define GICD_REGS_GICD_AFFINITY2_181_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_181_LEN    8
#define GICD_REGS_GICD_AFFINITY1_181_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_181_LEN    8
#define GICD_REGS_GICD_AFFINITY0_181_OFFSET 0

#define GICD_REGS_GICD_IRM_182_LEN          1
#define GICD_REGS_GICD_IRM_182_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_182_LEN    8
#define GICD_REGS_GICD_AFFINITY2_182_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_182_LEN    8
#define GICD_REGS_GICD_AFFINITY1_182_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_182_LEN    8
#define GICD_REGS_GICD_AFFINITY0_182_OFFSET 0

#define GICD_REGS_GICD_IRM_183_LEN          1
#define GICD_REGS_GICD_IRM_183_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_183_LEN    8
#define GICD_REGS_GICD_AFFINITY2_183_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_183_LEN    8
#define GICD_REGS_GICD_AFFINITY1_183_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_183_LEN    8
#define GICD_REGS_GICD_AFFINITY0_183_OFFSET 0

#define GICD_REGS_GICD_IRM_184_LEN          1
#define GICD_REGS_GICD_IRM_184_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_184_LEN    8
#define GICD_REGS_GICD_AFFINITY2_184_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_184_LEN    8
#define GICD_REGS_GICD_AFFINITY1_184_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_184_LEN    8
#define GICD_REGS_GICD_AFFINITY0_184_OFFSET 0

#define GICD_REGS_GICD_IRM_185_LEN          1
#define GICD_REGS_GICD_IRM_185_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_185_LEN    8
#define GICD_REGS_GICD_AFFINITY2_185_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_185_LEN    8
#define GICD_REGS_GICD_AFFINITY1_185_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_185_LEN    8
#define GICD_REGS_GICD_AFFINITY0_185_OFFSET 0

#define GICD_REGS_GICD_IRM_186_LEN          1
#define GICD_REGS_GICD_IRM_186_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_186_LEN    8
#define GICD_REGS_GICD_AFFINITY2_186_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_186_LEN    8
#define GICD_REGS_GICD_AFFINITY1_186_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_186_LEN    8
#define GICD_REGS_GICD_AFFINITY0_186_OFFSET 0

#define GICD_REGS_GICD_IRM_187_LEN          1
#define GICD_REGS_GICD_IRM_187_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_187_LEN    8
#define GICD_REGS_GICD_AFFINITY2_187_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_187_LEN    8
#define GICD_REGS_GICD_AFFINITY1_187_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_187_LEN    8
#define GICD_REGS_GICD_AFFINITY0_187_OFFSET 0

#define GICD_REGS_GICD_IRM_188_LEN          1
#define GICD_REGS_GICD_IRM_188_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_188_LEN    8
#define GICD_REGS_GICD_AFFINITY2_188_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_188_LEN    8
#define GICD_REGS_GICD_AFFINITY1_188_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_188_LEN    8
#define GICD_REGS_GICD_AFFINITY0_188_OFFSET 0

#define GICD_REGS_GICD_IRM_189_LEN          1
#define GICD_REGS_GICD_IRM_189_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_189_LEN    8
#define GICD_REGS_GICD_AFFINITY2_189_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_189_LEN    8
#define GICD_REGS_GICD_AFFINITY1_189_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_189_LEN    8
#define GICD_REGS_GICD_AFFINITY0_189_OFFSET 0

#define GICD_REGS_GICD_IRM_190_LEN          1
#define GICD_REGS_GICD_IRM_190_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_190_LEN    8
#define GICD_REGS_GICD_AFFINITY2_190_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_190_LEN    8
#define GICD_REGS_GICD_AFFINITY1_190_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_190_LEN    8
#define GICD_REGS_GICD_AFFINITY0_190_OFFSET 0

#define GICD_REGS_GICD_IRM_191_LEN          1
#define GICD_REGS_GICD_IRM_191_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_191_LEN    8
#define GICD_REGS_GICD_AFFINITY2_191_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_191_LEN    8
#define GICD_REGS_GICD_AFFINITY1_191_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_191_LEN    8
#define GICD_REGS_GICD_AFFINITY0_191_OFFSET 0

#define GICD_REGS_GICD_IRM_192_LEN          1
#define GICD_REGS_GICD_IRM_192_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_192_LEN    8
#define GICD_REGS_GICD_AFFINITY2_192_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_192_LEN    8
#define GICD_REGS_GICD_AFFINITY1_192_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_192_LEN    8
#define GICD_REGS_GICD_AFFINITY0_192_OFFSET 0

#define GICD_REGS_GICD_IRM_193_LEN          1
#define GICD_REGS_GICD_IRM_193_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_193_LEN    8
#define GICD_REGS_GICD_AFFINITY2_193_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_193_LEN    8
#define GICD_REGS_GICD_AFFINITY1_193_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_193_LEN    8
#define GICD_REGS_GICD_AFFINITY0_193_OFFSET 0

#define GICD_REGS_GICD_IRM_194_LEN          1
#define GICD_REGS_GICD_IRM_194_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_194_LEN    8
#define GICD_REGS_GICD_AFFINITY2_194_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_194_LEN    8
#define GICD_REGS_GICD_AFFINITY1_194_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_194_LEN    8
#define GICD_REGS_GICD_AFFINITY0_194_OFFSET 0

#define GICD_REGS_GICD_IRM_195_LEN          1
#define GICD_REGS_GICD_IRM_195_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_195_LEN    8
#define GICD_REGS_GICD_AFFINITY2_195_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_195_LEN    8
#define GICD_REGS_GICD_AFFINITY1_195_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_195_LEN    8
#define GICD_REGS_GICD_AFFINITY0_195_OFFSET 0

#define GICD_REGS_GICD_IRM_196_LEN          1
#define GICD_REGS_GICD_IRM_196_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_196_LEN    8
#define GICD_REGS_GICD_AFFINITY2_196_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_196_LEN    8
#define GICD_REGS_GICD_AFFINITY1_196_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_196_LEN    8
#define GICD_REGS_GICD_AFFINITY0_196_OFFSET 0

#define GICD_REGS_GICD_IRM_197_LEN          1
#define GICD_REGS_GICD_IRM_197_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_197_LEN    8
#define GICD_REGS_GICD_AFFINITY2_197_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_197_LEN    8
#define GICD_REGS_GICD_AFFINITY1_197_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_197_LEN    8
#define GICD_REGS_GICD_AFFINITY0_197_OFFSET 0

#define GICD_REGS_GICD_IRM_198_LEN          1
#define GICD_REGS_GICD_IRM_198_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_198_LEN    8
#define GICD_REGS_GICD_AFFINITY2_198_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_198_LEN    8
#define GICD_REGS_GICD_AFFINITY1_198_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_198_LEN    8
#define GICD_REGS_GICD_AFFINITY0_198_OFFSET 0

#define GICD_REGS_GICD_IRM_199_LEN          1
#define GICD_REGS_GICD_IRM_199_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_199_LEN    8
#define GICD_REGS_GICD_AFFINITY2_199_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_199_LEN    8
#define GICD_REGS_GICD_AFFINITY1_199_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_199_LEN    8
#define GICD_REGS_GICD_AFFINITY0_199_OFFSET 0

#define GICD_REGS_GICD_IRM_200_LEN          1
#define GICD_REGS_GICD_IRM_200_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_200_LEN    8
#define GICD_REGS_GICD_AFFINITY2_200_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_200_LEN    8
#define GICD_REGS_GICD_AFFINITY1_200_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_200_LEN    8
#define GICD_REGS_GICD_AFFINITY0_200_OFFSET 0

#define GICD_REGS_GICD_IRM_201_LEN          1
#define GICD_REGS_GICD_IRM_201_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_201_LEN    8
#define GICD_REGS_GICD_AFFINITY2_201_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_201_LEN    8
#define GICD_REGS_GICD_AFFINITY1_201_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_201_LEN    8
#define GICD_REGS_GICD_AFFINITY0_201_OFFSET 0

#define GICD_REGS_GICD_IRM_202_LEN          1
#define GICD_REGS_GICD_IRM_202_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_202_LEN    8
#define GICD_REGS_GICD_AFFINITY2_202_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_202_LEN    8
#define GICD_REGS_GICD_AFFINITY1_202_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_202_LEN    8
#define GICD_REGS_GICD_AFFINITY0_202_OFFSET 0

#define GICD_REGS_GICD_IRM_203_LEN          1
#define GICD_REGS_GICD_IRM_203_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_203_LEN    8
#define GICD_REGS_GICD_AFFINITY2_203_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_203_LEN    8
#define GICD_REGS_GICD_AFFINITY1_203_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_203_LEN    8
#define GICD_REGS_GICD_AFFINITY0_203_OFFSET 0

#define GICD_REGS_GICD_IRM_204_LEN          1
#define GICD_REGS_GICD_IRM_204_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_204_LEN    8
#define GICD_REGS_GICD_AFFINITY2_204_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_204_LEN    8
#define GICD_REGS_GICD_AFFINITY1_204_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_204_LEN    8
#define GICD_REGS_GICD_AFFINITY0_204_OFFSET 0

#define GICD_REGS_GICD_IRM_205_LEN          1
#define GICD_REGS_GICD_IRM_205_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_205_LEN    8
#define GICD_REGS_GICD_AFFINITY2_205_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_205_LEN    8
#define GICD_REGS_GICD_AFFINITY1_205_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_205_LEN    8
#define GICD_REGS_GICD_AFFINITY0_205_OFFSET 0

#define GICD_REGS_GICD_IRM_206_LEN          1
#define GICD_REGS_GICD_IRM_206_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_206_LEN    8
#define GICD_REGS_GICD_AFFINITY2_206_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_206_LEN    8
#define GICD_REGS_GICD_AFFINITY1_206_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_206_LEN    8
#define GICD_REGS_GICD_AFFINITY0_206_OFFSET 0

#define GICD_REGS_GICD_IRM_207_LEN          1
#define GICD_REGS_GICD_IRM_207_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_207_LEN    8
#define GICD_REGS_GICD_AFFINITY2_207_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_207_LEN    8
#define GICD_REGS_GICD_AFFINITY1_207_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_207_LEN    8
#define GICD_REGS_GICD_AFFINITY0_207_OFFSET 0

#define GICD_REGS_GICD_IRM_208_LEN          1
#define GICD_REGS_GICD_IRM_208_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_208_LEN    8
#define GICD_REGS_GICD_AFFINITY2_208_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_208_LEN    8
#define GICD_REGS_GICD_AFFINITY1_208_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_208_LEN    8
#define GICD_REGS_GICD_AFFINITY0_208_OFFSET 0

#define GICD_REGS_GICD_IRM_209_LEN          1
#define GICD_REGS_GICD_IRM_209_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_209_LEN    8
#define GICD_REGS_GICD_AFFINITY2_209_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_209_LEN    8
#define GICD_REGS_GICD_AFFINITY1_209_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_209_LEN    8
#define GICD_REGS_GICD_AFFINITY0_209_OFFSET 0

#define GICD_REGS_GICD_IRM_210_LEN          1
#define GICD_REGS_GICD_IRM_210_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_210_LEN    8
#define GICD_REGS_GICD_AFFINITY2_210_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_210_LEN    8
#define GICD_REGS_GICD_AFFINITY1_210_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_210_LEN    8
#define GICD_REGS_GICD_AFFINITY0_210_OFFSET 0

#define GICD_REGS_GICD_IRM_211_LEN          1
#define GICD_REGS_GICD_IRM_211_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_211_LEN    8
#define GICD_REGS_GICD_AFFINITY2_211_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_211_LEN    8
#define GICD_REGS_GICD_AFFINITY1_211_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_211_LEN    8
#define GICD_REGS_GICD_AFFINITY0_211_OFFSET 0

#define GICD_REGS_GICD_IRM_212_LEN          1
#define GICD_REGS_GICD_IRM_212_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_212_LEN    8
#define GICD_REGS_GICD_AFFINITY2_212_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_212_LEN    8
#define GICD_REGS_GICD_AFFINITY1_212_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_212_LEN    8
#define GICD_REGS_GICD_AFFINITY0_212_OFFSET 0

#define GICD_REGS_GICD_IRM_213_LEN          1
#define GICD_REGS_GICD_IRM_213_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_213_LEN    8
#define GICD_REGS_GICD_AFFINITY2_213_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_213_LEN    8
#define GICD_REGS_GICD_AFFINITY1_213_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_213_LEN    8
#define GICD_REGS_GICD_AFFINITY0_213_OFFSET 0

#define GICD_REGS_GICD_IRM_214_LEN          1
#define GICD_REGS_GICD_IRM_214_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_214_LEN    8
#define GICD_REGS_GICD_AFFINITY2_214_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_214_LEN    8
#define GICD_REGS_GICD_AFFINITY1_214_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_214_LEN    8
#define GICD_REGS_GICD_AFFINITY0_214_OFFSET 0

#define GICD_REGS_GICD_IRM_215_LEN          1
#define GICD_REGS_GICD_IRM_215_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_215_LEN    8
#define GICD_REGS_GICD_AFFINITY2_215_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_215_LEN    8
#define GICD_REGS_GICD_AFFINITY1_215_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_215_LEN    8
#define GICD_REGS_GICD_AFFINITY0_215_OFFSET 0

#define GICD_REGS_GICD_IRM_216_LEN          1
#define GICD_REGS_GICD_IRM_216_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_216_LEN    8
#define GICD_REGS_GICD_AFFINITY2_216_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_216_LEN    8
#define GICD_REGS_GICD_AFFINITY1_216_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_216_LEN    8
#define GICD_REGS_GICD_AFFINITY0_216_OFFSET 0

#define GICD_REGS_GICD_IRM_217_LEN          1
#define GICD_REGS_GICD_IRM_217_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_217_LEN    8
#define GICD_REGS_GICD_AFFINITY2_217_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_217_LEN    8
#define GICD_REGS_GICD_AFFINITY1_217_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_217_LEN    8
#define GICD_REGS_GICD_AFFINITY0_217_OFFSET 0

#define GICD_REGS_GICD_IRM_218_LEN          1
#define GICD_REGS_GICD_IRM_218_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_218_LEN    8
#define GICD_REGS_GICD_AFFINITY2_218_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_218_LEN    8
#define GICD_REGS_GICD_AFFINITY1_218_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_218_LEN    8
#define GICD_REGS_GICD_AFFINITY0_218_OFFSET 0

#define GICD_REGS_GICD_IRM_219_LEN          1
#define GICD_REGS_GICD_IRM_219_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_219_LEN    8
#define GICD_REGS_GICD_AFFINITY2_219_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_219_LEN    8
#define GICD_REGS_GICD_AFFINITY1_219_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_219_LEN    8
#define GICD_REGS_GICD_AFFINITY0_219_OFFSET 0

#define GICD_REGS_GICD_IRM_220_LEN          1
#define GICD_REGS_GICD_IRM_220_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_220_LEN    8
#define GICD_REGS_GICD_AFFINITY2_220_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_220_LEN    8
#define GICD_REGS_GICD_AFFINITY1_220_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_220_LEN    8
#define GICD_REGS_GICD_AFFINITY0_220_OFFSET 0

#define GICD_REGS_GICD_IRM_221_LEN          1
#define GICD_REGS_GICD_IRM_221_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_221_LEN    8
#define GICD_REGS_GICD_AFFINITY2_221_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_221_LEN    8
#define GICD_REGS_GICD_AFFINITY1_221_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_221_LEN    8
#define GICD_REGS_GICD_AFFINITY0_221_OFFSET 0

#define GICD_REGS_GICD_IRM_222_LEN          1
#define GICD_REGS_GICD_IRM_222_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_222_LEN    8
#define GICD_REGS_GICD_AFFINITY2_222_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_222_LEN    8
#define GICD_REGS_GICD_AFFINITY1_222_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_222_LEN    8
#define GICD_REGS_GICD_AFFINITY0_222_OFFSET 0

#define GICD_REGS_GICD_IRM_223_LEN          1
#define GICD_REGS_GICD_IRM_223_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_223_LEN    8
#define GICD_REGS_GICD_AFFINITY2_223_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_223_LEN    8
#define GICD_REGS_GICD_AFFINITY1_223_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_223_LEN    8
#define GICD_REGS_GICD_AFFINITY0_223_OFFSET 0

#define GICD_REGS_GICD_IRM_224_LEN          1
#define GICD_REGS_GICD_IRM_224_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_224_LEN    8
#define GICD_REGS_GICD_AFFINITY2_224_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_224_LEN    8
#define GICD_REGS_GICD_AFFINITY1_224_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_224_LEN    8
#define GICD_REGS_GICD_AFFINITY0_224_OFFSET 0

#define GICD_REGS_GICD_IRM_225_LEN          1
#define GICD_REGS_GICD_IRM_225_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_225_LEN    8
#define GICD_REGS_GICD_AFFINITY2_225_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_225_LEN    8
#define GICD_REGS_GICD_AFFINITY1_225_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_225_LEN    8
#define GICD_REGS_GICD_AFFINITY0_225_OFFSET 0

#define GICD_REGS_GICD_IRM_226_LEN          1
#define GICD_REGS_GICD_IRM_226_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_226_LEN    8
#define GICD_REGS_GICD_AFFINITY2_226_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_226_LEN    8
#define GICD_REGS_GICD_AFFINITY1_226_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_226_LEN    8
#define GICD_REGS_GICD_AFFINITY0_226_OFFSET 0

#define GICD_REGS_GICD_IRM_227_LEN          1
#define GICD_REGS_GICD_IRM_227_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_227_LEN    8
#define GICD_REGS_GICD_AFFINITY2_227_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_227_LEN    8
#define GICD_REGS_GICD_AFFINITY1_227_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_227_LEN    8
#define GICD_REGS_GICD_AFFINITY0_227_OFFSET 0

#define GICD_REGS_GICD_IRM_228_LEN          1
#define GICD_REGS_GICD_IRM_228_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_228_LEN    8
#define GICD_REGS_GICD_AFFINITY2_228_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_228_LEN    8
#define GICD_REGS_GICD_AFFINITY1_228_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_228_LEN    8
#define GICD_REGS_GICD_AFFINITY0_228_OFFSET 0

#define GICD_REGS_GICD_IRM_229_LEN          1
#define GICD_REGS_GICD_IRM_229_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_229_LEN    8
#define GICD_REGS_GICD_AFFINITY2_229_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_229_LEN    8
#define GICD_REGS_GICD_AFFINITY1_229_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_229_LEN    8
#define GICD_REGS_GICD_AFFINITY0_229_OFFSET 0

#define GICD_REGS_GICD_IRM_230_LEN          1
#define GICD_REGS_GICD_IRM_230_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_230_LEN    8
#define GICD_REGS_GICD_AFFINITY2_230_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_230_LEN    8
#define GICD_REGS_GICD_AFFINITY1_230_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_230_LEN    8
#define GICD_REGS_GICD_AFFINITY0_230_OFFSET 0

#define GICD_REGS_GICD_IRM_231_LEN          1
#define GICD_REGS_GICD_IRM_231_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_231_LEN    8
#define GICD_REGS_GICD_AFFINITY2_231_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_231_LEN    8
#define GICD_REGS_GICD_AFFINITY1_231_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_231_LEN    8
#define GICD_REGS_GICD_AFFINITY0_231_OFFSET 0

#define GICD_REGS_GICD_IRM_232_LEN          1
#define GICD_REGS_GICD_IRM_232_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_232_LEN    8
#define GICD_REGS_GICD_AFFINITY2_232_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_232_LEN    8
#define GICD_REGS_GICD_AFFINITY1_232_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_232_LEN    8
#define GICD_REGS_GICD_AFFINITY0_232_OFFSET 0

#define GICD_REGS_GICD_IRM_233_LEN          1
#define GICD_REGS_GICD_IRM_233_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_233_LEN    8
#define GICD_REGS_GICD_AFFINITY2_233_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_233_LEN    8
#define GICD_REGS_GICD_AFFINITY1_233_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_233_LEN    8
#define GICD_REGS_GICD_AFFINITY0_233_OFFSET 0

#define GICD_REGS_GICD_IRM_234_LEN          1
#define GICD_REGS_GICD_IRM_234_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_234_LEN    8
#define GICD_REGS_GICD_AFFINITY2_234_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_234_LEN    8
#define GICD_REGS_GICD_AFFINITY1_234_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_234_LEN    8
#define GICD_REGS_GICD_AFFINITY0_234_OFFSET 0

#define GICD_REGS_GICD_IRM_235_LEN          1
#define GICD_REGS_GICD_IRM_235_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_235_LEN    8
#define GICD_REGS_GICD_AFFINITY2_235_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_235_LEN    8
#define GICD_REGS_GICD_AFFINITY1_235_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_235_LEN    8
#define GICD_REGS_GICD_AFFINITY0_235_OFFSET 0

#define GICD_REGS_GICD_IRM_236_LEN          1
#define GICD_REGS_GICD_IRM_236_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_236_LEN    8
#define GICD_REGS_GICD_AFFINITY2_236_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_236_LEN    8
#define GICD_REGS_GICD_AFFINITY1_236_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_236_LEN    8
#define GICD_REGS_GICD_AFFINITY0_236_OFFSET 0

#define GICD_REGS_GICD_IRM_237_LEN          1
#define GICD_REGS_GICD_IRM_237_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_237_LEN    8
#define GICD_REGS_GICD_AFFINITY2_237_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_237_LEN    8
#define GICD_REGS_GICD_AFFINITY1_237_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_237_LEN    8
#define GICD_REGS_GICD_AFFINITY0_237_OFFSET 0

#define GICD_REGS_GICD_IRM_238_LEN          1
#define GICD_REGS_GICD_IRM_238_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_238_LEN    8
#define GICD_REGS_GICD_AFFINITY2_238_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_238_LEN    8
#define GICD_REGS_GICD_AFFINITY1_238_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_238_LEN    8
#define GICD_REGS_GICD_AFFINITY0_238_OFFSET 0

#define GICD_REGS_GICD_IRM_239_LEN          1
#define GICD_REGS_GICD_IRM_239_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_239_LEN    8
#define GICD_REGS_GICD_AFFINITY2_239_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_239_LEN    8
#define GICD_REGS_GICD_AFFINITY1_239_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_239_LEN    8
#define GICD_REGS_GICD_AFFINITY0_239_OFFSET 0

#define GICD_REGS_GICD_IRM_240_LEN          1
#define GICD_REGS_GICD_IRM_240_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_240_LEN    8
#define GICD_REGS_GICD_AFFINITY2_240_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_240_LEN    8
#define GICD_REGS_GICD_AFFINITY1_240_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_240_LEN    8
#define GICD_REGS_GICD_AFFINITY0_240_OFFSET 0

#define GICD_REGS_GICD_IRM_241_LEN          1
#define GICD_REGS_GICD_IRM_241_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_241_LEN    8
#define GICD_REGS_GICD_AFFINITY2_241_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_241_LEN    8
#define GICD_REGS_GICD_AFFINITY1_241_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_241_LEN    8
#define GICD_REGS_GICD_AFFINITY0_241_OFFSET 0

#define GICD_REGS_GICD_IRM_242_LEN          1
#define GICD_REGS_GICD_IRM_242_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_242_LEN    8
#define GICD_REGS_GICD_AFFINITY2_242_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_242_LEN    8
#define GICD_REGS_GICD_AFFINITY1_242_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_242_LEN    8
#define GICD_REGS_GICD_AFFINITY0_242_OFFSET 0

#define GICD_REGS_GICD_IRM_243_LEN          1
#define GICD_REGS_GICD_IRM_243_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_243_LEN    8
#define GICD_REGS_GICD_AFFINITY2_243_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_243_LEN    8
#define GICD_REGS_GICD_AFFINITY1_243_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_243_LEN    8
#define GICD_REGS_GICD_AFFINITY0_243_OFFSET 0

#define GICD_REGS_GICD_IRM_244_LEN          1
#define GICD_REGS_GICD_IRM_244_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_244_LEN    8
#define GICD_REGS_GICD_AFFINITY2_244_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_244_LEN    8
#define GICD_REGS_GICD_AFFINITY1_244_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_244_LEN    8
#define GICD_REGS_GICD_AFFINITY0_244_OFFSET 0

#define GICD_REGS_GICD_IRM_245_LEN          1
#define GICD_REGS_GICD_IRM_245_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_245_LEN    8
#define GICD_REGS_GICD_AFFINITY2_245_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_245_LEN    8
#define GICD_REGS_GICD_AFFINITY1_245_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_245_LEN    8
#define GICD_REGS_GICD_AFFINITY0_245_OFFSET 0

#define GICD_REGS_GICD_IRM_246_LEN          1
#define GICD_REGS_GICD_IRM_246_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_246_LEN    8
#define GICD_REGS_GICD_AFFINITY2_246_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_246_LEN    8
#define GICD_REGS_GICD_AFFINITY1_246_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_246_LEN    8
#define GICD_REGS_GICD_AFFINITY0_246_OFFSET 0

#define GICD_REGS_GICD_IRM_247_LEN          1
#define GICD_REGS_GICD_IRM_247_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_247_LEN    8
#define GICD_REGS_GICD_AFFINITY2_247_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_247_LEN    8
#define GICD_REGS_GICD_AFFINITY1_247_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_247_LEN    8
#define GICD_REGS_GICD_AFFINITY0_247_OFFSET 0

#define GICD_REGS_GICD_IRM_248_LEN          1
#define GICD_REGS_GICD_IRM_248_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_248_LEN    8
#define GICD_REGS_GICD_AFFINITY2_248_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_248_LEN    8
#define GICD_REGS_GICD_AFFINITY1_248_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_248_LEN    8
#define GICD_REGS_GICD_AFFINITY0_248_OFFSET 0

#define GICD_REGS_GICD_IRM_249_LEN          1
#define GICD_REGS_GICD_IRM_249_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_249_LEN    8
#define GICD_REGS_GICD_AFFINITY2_249_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_249_LEN    8
#define GICD_REGS_GICD_AFFINITY1_249_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_249_LEN    8
#define GICD_REGS_GICD_AFFINITY0_249_OFFSET 0

#define GICD_REGS_GICD_IRM_250_LEN          1
#define GICD_REGS_GICD_IRM_250_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_250_LEN    8
#define GICD_REGS_GICD_AFFINITY2_250_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_250_LEN    8
#define GICD_REGS_GICD_AFFINITY1_250_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_250_LEN    8
#define GICD_REGS_GICD_AFFINITY0_250_OFFSET 0

#define GICD_REGS_GICD_IRM_251_LEN          1
#define GICD_REGS_GICD_IRM_251_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_251_LEN    8
#define GICD_REGS_GICD_AFFINITY2_251_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_251_LEN    8
#define GICD_REGS_GICD_AFFINITY1_251_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_251_LEN    8
#define GICD_REGS_GICD_AFFINITY0_251_OFFSET 0

#define GICD_REGS_GICD_IRM_252_LEN          1
#define GICD_REGS_GICD_IRM_252_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_252_LEN    8
#define GICD_REGS_GICD_AFFINITY2_252_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_252_LEN    8
#define GICD_REGS_GICD_AFFINITY1_252_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_252_LEN    8
#define GICD_REGS_GICD_AFFINITY0_252_OFFSET 0

#define GICD_REGS_GICD_IRM_253_LEN          1
#define GICD_REGS_GICD_IRM_253_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_253_LEN    8
#define GICD_REGS_GICD_AFFINITY2_253_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_253_LEN    8
#define GICD_REGS_GICD_AFFINITY1_253_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_253_LEN    8
#define GICD_REGS_GICD_AFFINITY0_253_OFFSET 0

#define GICD_REGS_GICD_IRM_254_LEN          1
#define GICD_REGS_GICD_IRM_254_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_254_LEN    8
#define GICD_REGS_GICD_AFFINITY2_254_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_254_LEN    8
#define GICD_REGS_GICD_AFFINITY1_254_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_254_LEN    8
#define GICD_REGS_GICD_AFFINITY0_254_OFFSET 0

#define GICD_REGS_GICD_IRM_255_LEN          1
#define GICD_REGS_GICD_IRM_255_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_255_LEN    8
#define GICD_REGS_GICD_AFFINITY2_255_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_255_LEN    8
#define GICD_REGS_GICD_AFFINITY1_255_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_255_LEN    8
#define GICD_REGS_GICD_AFFINITY0_255_OFFSET 0

#define GICD_REGS_GICD_IRM_256_LEN          1
#define GICD_REGS_GICD_IRM_256_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_256_LEN    8
#define GICD_REGS_GICD_AFFINITY2_256_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_256_LEN    8
#define GICD_REGS_GICD_AFFINITY1_256_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_256_LEN    8
#define GICD_REGS_GICD_AFFINITY0_256_OFFSET 0

#define GICD_REGS_GICD_IRM_257_LEN          1
#define GICD_REGS_GICD_IRM_257_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_257_LEN    8
#define GICD_REGS_GICD_AFFINITY2_257_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_257_LEN    8
#define GICD_REGS_GICD_AFFINITY1_257_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_257_LEN    8
#define GICD_REGS_GICD_AFFINITY0_257_OFFSET 0

#define GICD_REGS_GICD_IRM_258_LEN          1
#define GICD_REGS_GICD_IRM_258_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_258_LEN    8
#define GICD_REGS_GICD_AFFINITY2_258_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_258_LEN    8
#define GICD_REGS_GICD_AFFINITY1_258_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_258_LEN    8
#define GICD_REGS_GICD_AFFINITY0_258_OFFSET 0

#define GICD_REGS_GICD_IRM_259_LEN          1
#define GICD_REGS_GICD_IRM_259_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_259_LEN    8
#define GICD_REGS_GICD_AFFINITY2_259_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_259_LEN    8
#define GICD_REGS_GICD_AFFINITY1_259_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_259_LEN    8
#define GICD_REGS_GICD_AFFINITY0_259_OFFSET 0

#define GICD_REGS_GICD_IRM_260_LEN          1
#define GICD_REGS_GICD_IRM_260_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_260_LEN    8
#define GICD_REGS_GICD_AFFINITY2_260_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_260_LEN    8
#define GICD_REGS_GICD_AFFINITY1_260_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_260_LEN    8
#define GICD_REGS_GICD_AFFINITY0_260_OFFSET 0

#define GICD_REGS_GICD_IRM_261_LEN          1
#define GICD_REGS_GICD_IRM_261_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_261_LEN    8
#define GICD_REGS_GICD_AFFINITY2_261_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_261_LEN    8
#define GICD_REGS_GICD_AFFINITY1_261_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_261_LEN    8
#define GICD_REGS_GICD_AFFINITY0_261_OFFSET 0

#define GICD_REGS_GICD_IRM_262_LEN          1
#define GICD_REGS_GICD_IRM_262_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_262_LEN    8
#define GICD_REGS_GICD_AFFINITY2_262_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_262_LEN    8
#define GICD_REGS_GICD_AFFINITY1_262_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_262_LEN    8
#define GICD_REGS_GICD_AFFINITY0_262_OFFSET 0

#define GICD_REGS_GICD_IRM_263_LEN          1
#define GICD_REGS_GICD_IRM_263_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_263_LEN    8
#define GICD_REGS_GICD_AFFINITY2_263_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_263_LEN    8
#define GICD_REGS_GICD_AFFINITY1_263_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_263_LEN    8
#define GICD_REGS_GICD_AFFINITY0_263_OFFSET 0

#define GICD_REGS_GICD_IRM_264_LEN          1
#define GICD_REGS_GICD_IRM_264_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_264_LEN    8
#define GICD_REGS_GICD_AFFINITY2_264_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_264_LEN    8
#define GICD_REGS_GICD_AFFINITY1_264_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_264_LEN    8
#define GICD_REGS_GICD_AFFINITY0_264_OFFSET 0

#define GICD_REGS_GICD_IRM_265_LEN          1
#define GICD_REGS_GICD_IRM_265_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_265_LEN    8
#define GICD_REGS_GICD_AFFINITY2_265_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_265_LEN    8
#define GICD_REGS_GICD_AFFINITY1_265_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_265_LEN    8
#define GICD_REGS_GICD_AFFINITY0_265_OFFSET 0

#define GICD_REGS_GICD_IRM_266_LEN          1
#define GICD_REGS_GICD_IRM_266_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_266_LEN    8
#define GICD_REGS_GICD_AFFINITY2_266_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_266_LEN    8
#define GICD_REGS_GICD_AFFINITY1_266_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_266_LEN    8
#define GICD_REGS_GICD_AFFINITY0_266_OFFSET 0

#define GICD_REGS_GICD_IRM_267_LEN          1
#define GICD_REGS_GICD_IRM_267_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_267_LEN    8
#define GICD_REGS_GICD_AFFINITY2_267_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_267_LEN    8
#define GICD_REGS_GICD_AFFINITY1_267_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_267_LEN    8
#define GICD_REGS_GICD_AFFINITY0_267_OFFSET 0

#define GICD_REGS_GICD_IRM_268_LEN          1
#define GICD_REGS_GICD_IRM_268_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_268_LEN    8
#define GICD_REGS_GICD_AFFINITY2_268_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_268_LEN    8
#define GICD_REGS_GICD_AFFINITY1_268_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_268_LEN    8
#define GICD_REGS_GICD_AFFINITY0_268_OFFSET 0

#define GICD_REGS_GICD_IRM_269_LEN          1
#define GICD_REGS_GICD_IRM_269_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_269_LEN    8
#define GICD_REGS_GICD_AFFINITY2_269_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_269_LEN    8
#define GICD_REGS_GICD_AFFINITY1_269_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_269_LEN    8
#define GICD_REGS_GICD_AFFINITY0_269_OFFSET 0

#define GICD_REGS_GICD_IRM_270_LEN          1
#define GICD_REGS_GICD_IRM_270_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_270_LEN    8
#define GICD_REGS_GICD_AFFINITY2_270_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_270_LEN    8
#define GICD_REGS_GICD_AFFINITY1_270_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_270_LEN    8
#define GICD_REGS_GICD_AFFINITY0_270_OFFSET 0

#define GICD_REGS_GICD_IRM_271_LEN          1
#define GICD_REGS_GICD_IRM_271_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_271_LEN    8
#define GICD_REGS_GICD_AFFINITY2_271_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_271_LEN    8
#define GICD_REGS_GICD_AFFINITY1_271_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_271_LEN    8
#define GICD_REGS_GICD_AFFINITY0_271_OFFSET 0

#define GICD_REGS_GICD_IRM_272_LEN          1
#define GICD_REGS_GICD_IRM_272_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_272_LEN    8
#define GICD_REGS_GICD_AFFINITY2_272_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_272_LEN    8
#define GICD_REGS_GICD_AFFINITY1_272_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_272_LEN    8
#define GICD_REGS_GICD_AFFINITY0_272_OFFSET 0

#define GICD_REGS_GICD_IRM_273_LEN          1
#define GICD_REGS_GICD_IRM_273_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_273_LEN    8
#define GICD_REGS_GICD_AFFINITY2_273_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_273_LEN    8
#define GICD_REGS_GICD_AFFINITY1_273_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_273_LEN    8
#define GICD_REGS_GICD_AFFINITY0_273_OFFSET 0

#define GICD_REGS_GICD_IRM_274_LEN          1
#define GICD_REGS_GICD_IRM_274_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_274_LEN    8
#define GICD_REGS_GICD_AFFINITY2_274_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_274_LEN    8
#define GICD_REGS_GICD_AFFINITY1_274_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_274_LEN    8
#define GICD_REGS_GICD_AFFINITY0_274_OFFSET 0

#define GICD_REGS_GICD_IRM_275_LEN          1
#define GICD_REGS_GICD_IRM_275_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_275_LEN    8
#define GICD_REGS_GICD_AFFINITY2_275_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_275_LEN    8
#define GICD_REGS_GICD_AFFINITY1_275_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_275_LEN    8
#define GICD_REGS_GICD_AFFINITY0_275_OFFSET 0

#define GICD_REGS_GICD_IRM_276_LEN          1
#define GICD_REGS_GICD_IRM_276_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_276_LEN    8
#define GICD_REGS_GICD_AFFINITY2_276_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_276_LEN    8
#define GICD_REGS_GICD_AFFINITY1_276_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_276_LEN    8
#define GICD_REGS_GICD_AFFINITY0_276_OFFSET 0

#define GICD_REGS_GICD_IRM_277_LEN          1
#define GICD_REGS_GICD_IRM_277_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_277_LEN    8
#define GICD_REGS_GICD_AFFINITY2_277_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_277_LEN    8
#define GICD_REGS_GICD_AFFINITY1_277_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_277_LEN    8
#define GICD_REGS_GICD_AFFINITY0_277_OFFSET 0

#define GICD_REGS_GICD_IRM_278_LEN          1
#define GICD_REGS_GICD_IRM_278_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_278_LEN    8
#define GICD_REGS_GICD_AFFINITY2_278_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_278_LEN    8
#define GICD_REGS_GICD_AFFINITY1_278_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_278_LEN    8
#define GICD_REGS_GICD_AFFINITY0_278_OFFSET 0

#define GICD_REGS_GICD_IRM_279_LEN          1
#define GICD_REGS_GICD_IRM_279_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_279_LEN    8
#define GICD_REGS_GICD_AFFINITY2_279_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_279_LEN    8
#define GICD_REGS_GICD_AFFINITY1_279_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_279_LEN    8
#define GICD_REGS_GICD_AFFINITY0_279_OFFSET 0

#define GICD_REGS_GICD_IRM_280_LEN          1
#define GICD_REGS_GICD_IRM_280_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_280_LEN    8
#define GICD_REGS_GICD_AFFINITY2_280_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_280_LEN    8
#define GICD_REGS_GICD_AFFINITY1_280_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_280_LEN    8
#define GICD_REGS_GICD_AFFINITY0_280_OFFSET 0

#define GICD_REGS_GICD_IRM_281_LEN          1
#define GICD_REGS_GICD_IRM_281_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_281_LEN    8
#define GICD_REGS_GICD_AFFINITY2_281_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_281_LEN    8
#define GICD_REGS_GICD_AFFINITY1_281_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_281_LEN    8
#define GICD_REGS_GICD_AFFINITY0_281_OFFSET 0

#define GICD_REGS_GICD_IRM_282_LEN          1
#define GICD_REGS_GICD_IRM_282_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_282_LEN    8
#define GICD_REGS_GICD_AFFINITY2_282_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_282_LEN    8
#define GICD_REGS_GICD_AFFINITY1_282_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_282_LEN    8
#define GICD_REGS_GICD_AFFINITY0_282_OFFSET 0

#define GICD_REGS_GICD_IRM_283_LEN          1
#define GICD_REGS_GICD_IRM_283_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_283_LEN    8
#define GICD_REGS_GICD_AFFINITY2_283_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_283_LEN    8
#define GICD_REGS_GICD_AFFINITY1_283_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_283_LEN    8
#define GICD_REGS_GICD_AFFINITY0_283_OFFSET 0

#define GICD_REGS_GICD_IRM_284_LEN          1
#define GICD_REGS_GICD_IRM_284_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_284_LEN    8
#define GICD_REGS_GICD_AFFINITY2_284_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_284_LEN    8
#define GICD_REGS_GICD_AFFINITY1_284_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_284_LEN    8
#define GICD_REGS_GICD_AFFINITY0_284_OFFSET 0

#define GICD_REGS_GICD_IRM_285_LEN          1
#define GICD_REGS_GICD_IRM_285_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_285_LEN    8
#define GICD_REGS_GICD_AFFINITY2_285_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_285_LEN    8
#define GICD_REGS_GICD_AFFINITY1_285_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_285_LEN    8
#define GICD_REGS_GICD_AFFINITY0_285_OFFSET 0

#define GICD_REGS_GICD_IRM_286_LEN          1
#define GICD_REGS_GICD_IRM_286_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_286_LEN    8
#define GICD_REGS_GICD_AFFINITY2_286_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_286_LEN    8
#define GICD_REGS_GICD_AFFINITY1_286_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_286_LEN    8
#define GICD_REGS_GICD_AFFINITY0_286_OFFSET 0

#define GICD_REGS_GICD_IRM_287_LEN          1
#define GICD_REGS_GICD_IRM_287_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_287_LEN    8
#define GICD_REGS_GICD_AFFINITY2_287_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_287_LEN    8
#define GICD_REGS_GICD_AFFINITY1_287_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_287_LEN    8
#define GICD_REGS_GICD_AFFINITY0_287_OFFSET 0

#define GICD_REGS_GICD_IRM_288_LEN          1
#define GICD_REGS_GICD_IRM_288_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_288_LEN    8
#define GICD_REGS_GICD_AFFINITY2_288_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_288_LEN    8
#define GICD_REGS_GICD_AFFINITY1_288_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_288_LEN    8
#define GICD_REGS_GICD_AFFINITY0_288_OFFSET 0

#define GICD_REGS_GICD_IRM_289_LEN          1
#define GICD_REGS_GICD_IRM_289_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_289_LEN    8
#define GICD_REGS_GICD_AFFINITY2_289_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_289_LEN    8
#define GICD_REGS_GICD_AFFINITY1_289_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_289_LEN    8
#define GICD_REGS_GICD_AFFINITY0_289_OFFSET 0

#define GICD_REGS_GICD_IRM_290_LEN          1
#define GICD_REGS_GICD_IRM_290_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_290_LEN    8
#define GICD_REGS_GICD_AFFINITY2_290_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_290_LEN    8
#define GICD_REGS_GICD_AFFINITY1_290_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_290_LEN    8
#define GICD_REGS_GICD_AFFINITY0_290_OFFSET 0

#define GICD_REGS_GICD_IRM_291_LEN          1
#define GICD_REGS_GICD_IRM_291_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_291_LEN    8
#define GICD_REGS_GICD_AFFINITY2_291_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_291_LEN    8
#define GICD_REGS_GICD_AFFINITY1_291_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_291_LEN    8
#define GICD_REGS_GICD_AFFINITY0_291_OFFSET 0

#define GICD_REGS_GICD_IRM_292_LEN          1
#define GICD_REGS_GICD_IRM_292_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_292_LEN    8
#define GICD_REGS_GICD_AFFINITY2_292_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_292_LEN    8
#define GICD_REGS_GICD_AFFINITY1_292_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_292_LEN    8
#define GICD_REGS_GICD_AFFINITY0_292_OFFSET 0

#define GICD_REGS_GICD_IRM_293_LEN          1
#define GICD_REGS_GICD_IRM_293_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_293_LEN    8
#define GICD_REGS_GICD_AFFINITY2_293_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_293_LEN    8
#define GICD_REGS_GICD_AFFINITY1_293_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_293_LEN    8
#define GICD_REGS_GICD_AFFINITY0_293_OFFSET 0

#define GICD_REGS_GICD_IRM_294_LEN          1
#define GICD_REGS_GICD_IRM_294_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_294_LEN    8
#define GICD_REGS_GICD_AFFINITY2_294_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_294_LEN    8
#define GICD_REGS_GICD_AFFINITY1_294_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_294_LEN    8
#define GICD_REGS_GICD_AFFINITY0_294_OFFSET 0

#define GICD_REGS_GICD_IRM_295_LEN          1
#define GICD_REGS_GICD_IRM_295_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_295_LEN    8
#define GICD_REGS_GICD_AFFINITY2_295_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_295_LEN    8
#define GICD_REGS_GICD_AFFINITY1_295_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_295_LEN    8
#define GICD_REGS_GICD_AFFINITY0_295_OFFSET 0

#define GICD_REGS_GICD_IRM_296_LEN          1
#define GICD_REGS_GICD_IRM_296_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_296_LEN    8
#define GICD_REGS_GICD_AFFINITY2_296_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_296_LEN    8
#define GICD_REGS_GICD_AFFINITY1_296_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_296_LEN    8
#define GICD_REGS_GICD_AFFINITY0_296_OFFSET 0

#define GICD_REGS_GICD_IRM_297_LEN          1
#define GICD_REGS_GICD_IRM_297_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_297_LEN    8
#define GICD_REGS_GICD_AFFINITY2_297_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_297_LEN    8
#define GICD_REGS_GICD_AFFINITY1_297_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_297_LEN    8
#define GICD_REGS_GICD_AFFINITY0_297_OFFSET 0

#define GICD_REGS_GICD_IRM_298_LEN          1
#define GICD_REGS_GICD_IRM_298_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_298_LEN    8
#define GICD_REGS_GICD_AFFINITY2_298_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_298_LEN    8
#define GICD_REGS_GICD_AFFINITY1_298_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_298_LEN    8
#define GICD_REGS_GICD_AFFINITY0_298_OFFSET 0

#define GICD_REGS_GICD_IRM_299_LEN          1
#define GICD_REGS_GICD_IRM_299_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_299_LEN    8
#define GICD_REGS_GICD_AFFINITY2_299_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_299_LEN    8
#define GICD_REGS_GICD_AFFINITY1_299_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_299_LEN    8
#define GICD_REGS_GICD_AFFINITY0_299_OFFSET 0

#define GICD_REGS_GICD_IRM_300_LEN          1
#define GICD_REGS_GICD_IRM_300_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_300_LEN    8
#define GICD_REGS_GICD_AFFINITY2_300_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_300_LEN    8
#define GICD_REGS_GICD_AFFINITY1_300_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_300_LEN    8
#define GICD_REGS_GICD_AFFINITY0_300_OFFSET 0

#define GICD_REGS_GICD_IRM_301_LEN          1
#define GICD_REGS_GICD_IRM_301_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_301_LEN    8
#define GICD_REGS_GICD_AFFINITY2_301_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_301_LEN    8
#define GICD_REGS_GICD_AFFINITY1_301_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_301_LEN    8
#define GICD_REGS_GICD_AFFINITY0_301_OFFSET 0

#define GICD_REGS_GICD_IRM_302_LEN          1
#define GICD_REGS_GICD_IRM_302_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_302_LEN    8
#define GICD_REGS_GICD_AFFINITY2_302_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_302_LEN    8
#define GICD_REGS_GICD_AFFINITY1_302_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_302_LEN    8
#define GICD_REGS_GICD_AFFINITY0_302_OFFSET 0

#define GICD_REGS_GICD_IRM_303_LEN          1
#define GICD_REGS_GICD_IRM_303_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_303_LEN    8
#define GICD_REGS_GICD_AFFINITY2_303_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_303_LEN    8
#define GICD_REGS_GICD_AFFINITY1_303_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_303_LEN    8
#define GICD_REGS_GICD_AFFINITY0_303_OFFSET 0

#define GICD_REGS_GICD_IRM_304_LEN          1
#define GICD_REGS_GICD_IRM_304_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_304_LEN    8
#define GICD_REGS_GICD_AFFINITY2_304_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_304_LEN    8
#define GICD_REGS_GICD_AFFINITY1_304_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_304_LEN    8
#define GICD_REGS_GICD_AFFINITY0_304_OFFSET 0

#define GICD_REGS_GICD_IRM_305_LEN          1
#define GICD_REGS_GICD_IRM_305_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_305_LEN    8
#define GICD_REGS_GICD_AFFINITY2_305_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_305_LEN    8
#define GICD_REGS_GICD_AFFINITY1_305_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_305_LEN    8
#define GICD_REGS_GICD_AFFINITY0_305_OFFSET 0

#define GICD_REGS_GICD_IRM_306_LEN          1
#define GICD_REGS_GICD_IRM_306_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_306_LEN    8
#define GICD_REGS_GICD_AFFINITY2_306_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_306_LEN    8
#define GICD_REGS_GICD_AFFINITY1_306_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_306_LEN    8
#define GICD_REGS_GICD_AFFINITY0_306_OFFSET 0

#define GICD_REGS_GICD_IRM_307_LEN          1
#define GICD_REGS_GICD_IRM_307_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_307_LEN    8
#define GICD_REGS_GICD_AFFINITY2_307_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_307_LEN    8
#define GICD_REGS_GICD_AFFINITY1_307_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_307_LEN    8
#define GICD_REGS_GICD_AFFINITY0_307_OFFSET 0

#define GICD_REGS_GICD_IRM_308_LEN          1
#define GICD_REGS_GICD_IRM_308_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_308_LEN    8
#define GICD_REGS_GICD_AFFINITY2_308_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_308_LEN    8
#define GICD_REGS_GICD_AFFINITY1_308_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_308_LEN    8
#define GICD_REGS_GICD_AFFINITY0_308_OFFSET 0

#define GICD_REGS_GICD_IRM_309_LEN          1
#define GICD_REGS_GICD_IRM_309_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_309_LEN    8
#define GICD_REGS_GICD_AFFINITY2_309_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_309_LEN    8
#define GICD_REGS_GICD_AFFINITY1_309_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_309_LEN    8
#define GICD_REGS_GICD_AFFINITY0_309_OFFSET 0

#define GICD_REGS_GICD_IRM_310_LEN          1
#define GICD_REGS_GICD_IRM_310_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_310_LEN    8
#define GICD_REGS_GICD_AFFINITY2_310_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_310_LEN    8
#define GICD_REGS_GICD_AFFINITY1_310_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_310_LEN    8
#define GICD_REGS_GICD_AFFINITY0_310_OFFSET 0

#define GICD_REGS_GICD_IRM_311_LEN          1
#define GICD_REGS_GICD_IRM_311_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_311_LEN    8
#define GICD_REGS_GICD_AFFINITY2_311_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_311_LEN    8
#define GICD_REGS_GICD_AFFINITY1_311_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_311_LEN    8
#define GICD_REGS_GICD_AFFINITY0_311_OFFSET 0

#define GICD_REGS_GICD_IRM_312_LEN          1
#define GICD_REGS_GICD_IRM_312_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_312_LEN    8
#define GICD_REGS_GICD_AFFINITY2_312_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_312_LEN    8
#define GICD_REGS_GICD_AFFINITY1_312_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_312_LEN    8
#define GICD_REGS_GICD_AFFINITY0_312_OFFSET 0

#define GICD_REGS_GICD_IRM_313_LEN          1
#define GICD_REGS_GICD_IRM_313_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_313_LEN    8
#define GICD_REGS_GICD_AFFINITY2_313_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_313_LEN    8
#define GICD_REGS_GICD_AFFINITY1_313_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_313_LEN    8
#define GICD_REGS_GICD_AFFINITY0_313_OFFSET 0

#define GICD_REGS_GICD_IRM_314_LEN          1
#define GICD_REGS_GICD_IRM_314_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_314_LEN    8
#define GICD_REGS_GICD_AFFINITY2_314_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_314_LEN    8
#define GICD_REGS_GICD_AFFINITY1_314_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_314_LEN    8
#define GICD_REGS_GICD_AFFINITY0_314_OFFSET 0

#define GICD_REGS_GICD_IRM_315_LEN          1
#define GICD_REGS_GICD_IRM_315_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_315_LEN    8
#define GICD_REGS_GICD_AFFINITY2_315_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_315_LEN    8
#define GICD_REGS_GICD_AFFINITY1_315_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_315_LEN    8
#define GICD_REGS_GICD_AFFINITY0_315_OFFSET 0

#define GICD_REGS_GICD_IRM_316_LEN          1
#define GICD_REGS_GICD_IRM_316_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_316_LEN    8
#define GICD_REGS_GICD_AFFINITY2_316_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_316_LEN    8
#define GICD_REGS_GICD_AFFINITY1_316_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_316_LEN    8
#define GICD_REGS_GICD_AFFINITY0_316_OFFSET 0

#define GICD_REGS_GICD_IRM_317_LEN          1
#define GICD_REGS_GICD_IRM_317_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_317_LEN    8
#define GICD_REGS_GICD_AFFINITY2_317_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_317_LEN    8
#define GICD_REGS_GICD_AFFINITY1_317_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_317_LEN    8
#define GICD_REGS_GICD_AFFINITY0_317_OFFSET 0

#define GICD_REGS_GICD_IRM_318_LEN          1
#define GICD_REGS_GICD_IRM_318_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_318_LEN    8
#define GICD_REGS_GICD_AFFINITY2_318_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_318_LEN    8
#define GICD_REGS_GICD_AFFINITY1_318_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_318_LEN    8
#define GICD_REGS_GICD_AFFINITY0_318_OFFSET 0

#define GICD_REGS_GICD_IRM_319_LEN          1
#define GICD_REGS_GICD_IRM_319_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_319_LEN    8
#define GICD_REGS_GICD_AFFINITY2_319_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_319_LEN    8
#define GICD_REGS_GICD_AFFINITY1_319_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_319_LEN    8
#define GICD_REGS_GICD_AFFINITY0_319_OFFSET 0

#define GICD_REGS_GICD_IRM_320_LEN          1
#define GICD_REGS_GICD_IRM_320_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_320_LEN    8
#define GICD_REGS_GICD_AFFINITY2_320_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_320_LEN    8
#define GICD_REGS_GICD_AFFINITY1_320_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_320_LEN    8
#define GICD_REGS_GICD_AFFINITY0_320_OFFSET 0

#define GICD_REGS_GICD_IRM_321_LEN          1
#define GICD_REGS_GICD_IRM_321_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_321_LEN    8
#define GICD_REGS_GICD_AFFINITY2_321_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_321_LEN    8
#define GICD_REGS_GICD_AFFINITY1_321_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_321_LEN    8
#define GICD_REGS_GICD_AFFINITY0_321_OFFSET 0

#define GICD_REGS_GICD_IRM_322_LEN          1
#define GICD_REGS_GICD_IRM_322_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_322_LEN    8
#define GICD_REGS_GICD_AFFINITY2_322_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_322_LEN    8
#define GICD_REGS_GICD_AFFINITY1_322_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_322_LEN    8
#define GICD_REGS_GICD_AFFINITY0_322_OFFSET 0

#define GICD_REGS_GICD_IRM_323_LEN          1
#define GICD_REGS_GICD_IRM_323_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_323_LEN    8
#define GICD_REGS_GICD_AFFINITY2_323_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_323_LEN    8
#define GICD_REGS_GICD_AFFINITY1_323_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_323_LEN    8
#define GICD_REGS_GICD_AFFINITY0_323_OFFSET 0

#define GICD_REGS_GICD_IRM_324_LEN          1
#define GICD_REGS_GICD_IRM_324_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_324_LEN    8
#define GICD_REGS_GICD_AFFINITY2_324_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_324_LEN    8
#define GICD_REGS_GICD_AFFINITY1_324_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_324_LEN    8
#define GICD_REGS_GICD_AFFINITY0_324_OFFSET 0

#define GICD_REGS_GICD_IRM_325_LEN          1
#define GICD_REGS_GICD_IRM_325_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_325_LEN    8
#define GICD_REGS_GICD_AFFINITY2_325_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_325_LEN    8
#define GICD_REGS_GICD_AFFINITY1_325_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_325_LEN    8
#define GICD_REGS_GICD_AFFINITY0_325_OFFSET 0

#define GICD_REGS_GICD_IRM_326_LEN          1
#define GICD_REGS_GICD_IRM_326_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_326_LEN    8
#define GICD_REGS_GICD_AFFINITY2_326_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_326_LEN    8
#define GICD_REGS_GICD_AFFINITY1_326_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_326_LEN    8
#define GICD_REGS_GICD_AFFINITY0_326_OFFSET 0

#define GICD_REGS_GICD_IRM_327_LEN          1
#define GICD_REGS_GICD_IRM_327_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_327_LEN    8
#define GICD_REGS_GICD_AFFINITY2_327_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_327_LEN    8
#define GICD_REGS_GICD_AFFINITY1_327_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_327_LEN    8
#define GICD_REGS_GICD_AFFINITY0_327_OFFSET 0

#define GICD_REGS_GICD_IRM_328_LEN          1
#define GICD_REGS_GICD_IRM_328_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_328_LEN    8
#define GICD_REGS_GICD_AFFINITY2_328_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_328_LEN    8
#define GICD_REGS_GICD_AFFINITY1_328_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_328_LEN    8
#define GICD_REGS_GICD_AFFINITY0_328_OFFSET 0

#define GICD_REGS_GICD_IRM_329_LEN          1
#define GICD_REGS_GICD_IRM_329_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_329_LEN    8
#define GICD_REGS_GICD_AFFINITY2_329_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_329_LEN    8
#define GICD_REGS_GICD_AFFINITY1_329_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_329_LEN    8
#define GICD_REGS_GICD_AFFINITY0_329_OFFSET 0

#define GICD_REGS_GICD_IRM_330_LEN          1
#define GICD_REGS_GICD_IRM_330_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_330_LEN    8
#define GICD_REGS_GICD_AFFINITY2_330_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_330_LEN    8
#define GICD_REGS_GICD_AFFINITY1_330_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_330_LEN    8
#define GICD_REGS_GICD_AFFINITY0_330_OFFSET 0

#define GICD_REGS_GICD_IRM_331_LEN          1
#define GICD_REGS_GICD_IRM_331_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_331_LEN    8
#define GICD_REGS_GICD_AFFINITY2_331_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_331_LEN    8
#define GICD_REGS_GICD_AFFINITY1_331_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_331_LEN    8
#define GICD_REGS_GICD_AFFINITY0_331_OFFSET 0

#define GICD_REGS_GICD_IRM_332_LEN          1
#define GICD_REGS_GICD_IRM_332_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_332_LEN    8
#define GICD_REGS_GICD_AFFINITY2_332_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_332_LEN    8
#define GICD_REGS_GICD_AFFINITY1_332_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_332_LEN    8
#define GICD_REGS_GICD_AFFINITY0_332_OFFSET 0

#define GICD_REGS_GICD_IRM_333_LEN          1
#define GICD_REGS_GICD_IRM_333_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_333_LEN    8
#define GICD_REGS_GICD_AFFINITY2_333_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_333_LEN    8
#define GICD_REGS_GICD_AFFINITY1_333_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_333_LEN    8
#define GICD_REGS_GICD_AFFINITY0_333_OFFSET 0

#define GICD_REGS_GICD_IRM_334_LEN          1
#define GICD_REGS_GICD_IRM_334_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_334_LEN    8
#define GICD_REGS_GICD_AFFINITY2_334_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_334_LEN    8
#define GICD_REGS_GICD_AFFINITY1_334_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_334_LEN    8
#define GICD_REGS_GICD_AFFINITY0_334_OFFSET 0

#define GICD_REGS_GICD_IRM_335_LEN          1
#define GICD_REGS_GICD_IRM_335_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_335_LEN    8
#define GICD_REGS_GICD_AFFINITY2_335_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_335_LEN    8
#define GICD_REGS_GICD_AFFINITY1_335_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_335_LEN    8
#define GICD_REGS_GICD_AFFINITY0_335_OFFSET 0

#define GICD_REGS_GICD_IRM_336_LEN          1
#define GICD_REGS_GICD_IRM_336_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_336_LEN    8
#define GICD_REGS_GICD_AFFINITY2_336_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_336_LEN    8
#define GICD_REGS_GICD_AFFINITY1_336_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_336_LEN    8
#define GICD_REGS_GICD_AFFINITY0_336_OFFSET 0

#define GICD_REGS_GICD_IRM_337_LEN          1
#define GICD_REGS_GICD_IRM_337_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_337_LEN    8
#define GICD_REGS_GICD_AFFINITY2_337_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_337_LEN    8
#define GICD_REGS_GICD_AFFINITY1_337_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_337_LEN    8
#define GICD_REGS_GICD_AFFINITY0_337_OFFSET 0

#define GICD_REGS_GICD_IRM_338_LEN          1
#define GICD_REGS_GICD_IRM_338_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_338_LEN    8
#define GICD_REGS_GICD_AFFINITY2_338_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_338_LEN    8
#define GICD_REGS_GICD_AFFINITY1_338_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_338_LEN    8
#define GICD_REGS_GICD_AFFINITY0_338_OFFSET 0

#define GICD_REGS_GICD_IRM_339_LEN          1
#define GICD_REGS_GICD_IRM_339_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_339_LEN    8
#define GICD_REGS_GICD_AFFINITY2_339_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_339_LEN    8
#define GICD_REGS_GICD_AFFINITY1_339_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_339_LEN    8
#define GICD_REGS_GICD_AFFINITY0_339_OFFSET 0

#define GICD_REGS_GICD_IRM_340_LEN          1
#define GICD_REGS_GICD_IRM_340_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_340_LEN    8
#define GICD_REGS_GICD_AFFINITY2_340_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_340_LEN    8
#define GICD_REGS_GICD_AFFINITY1_340_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_340_LEN    8
#define GICD_REGS_GICD_AFFINITY0_340_OFFSET 0

#define GICD_REGS_GICD_IRM_341_LEN          1
#define GICD_REGS_GICD_IRM_341_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_341_LEN    8
#define GICD_REGS_GICD_AFFINITY2_341_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_341_LEN    8
#define GICD_REGS_GICD_AFFINITY1_341_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_341_LEN    8
#define GICD_REGS_GICD_AFFINITY0_341_OFFSET 0

#define GICD_REGS_GICD_IRM_342_LEN          1
#define GICD_REGS_GICD_IRM_342_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_342_LEN    8
#define GICD_REGS_GICD_AFFINITY2_342_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_342_LEN    8
#define GICD_REGS_GICD_AFFINITY1_342_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_342_LEN    8
#define GICD_REGS_GICD_AFFINITY0_342_OFFSET 0

#define GICD_REGS_GICD_IRM_343_LEN          1
#define GICD_REGS_GICD_IRM_343_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_343_LEN    8
#define GICD_REGS_GICD_AFFINITY2_343_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_343_LEN    8
#define GICD_REGS_GICD_AFFINITY1_343_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_343_LEN    8
#define GICD_REGS_GICD_AFFINITY0_343_OFFSET 0

#define GICD_REGS_GICD_IRM_344_LEN          1
#define GICD_REGS_GICD_IRM_344_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_344_LEN    8
#define GICD_REGS_GICD_AFFINITY2_344_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_344_LEN    8
#define GICD_REGS_GICD_AFFINITY1_344_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_344_LEN    8
#define GICD_REGS_GICD_AFFINITY0_344_OFFSET 0

#define GICD_REGS_GICD_IRM_345_LEN          1
#define GICD_REGS_GICD_IRM_345_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_345_LEN    8
#define GICD_REGS_GICD_AFFINITY2_345_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_345_LEN    8
#define GICD_REGS_GICD_AFFINITY1_345_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_345_LEN    8
#define GICD_REGS_GICD_AFFINITY0_345_OFFSET 0

#define GICD_REGS_GICD_IRM_346_LEN          1
#define GICD_REGS_GICD_IRM_346_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_346_LEN    8
#define GICD_REGS_GICD_AFFINITY2_346_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_346_LEN    8
#define GICD_REGS_GICD_AFFINITY1_346_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_346_LEN    8
#define GICD_REGS_GICD_AFFINITY0_346_OFFSET 0

#define GICD_REGS_GICD_IRM_347_LEN          1
#define GICD_REGS_GICD_IRM_347_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_347_LEN    8
#define GICD_REGS_GICD_AFFINITY2_347_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_347_LEN    8
#define GICD_REGS_GICD_AFFINITY1_347_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_347_LEN    8
#define GICD_REGS_GICD_AFFINITY0_347_OFFSET 0

#define GICD_REGS_GICD_IRM_348_LEN          1
#define GICD_REGS_GICD_IRM_348_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_348_LEN    8
#define GICD_REGS_GICD_AFFINITY2_348_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_348_LEN    8
#define GICD_REGS_GICD_AFFINITY1_348_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_348_LEN    8
#define GICD_REGS_GICD_AFFINITY0_348_OFFSET 0

#define GICD_REGS_GICD_IRM_349_LEN          1
#define GICD_REGS_GICD_IRM_349_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_349_LEN    8
#define GICD_REGS_GICD_AFFINITY2_349_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_349_LEN    8
#define GICD_REGS_GICD_AFFINITY1_349_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_349_LEN    8
#define GICD_REGS_GICD_AFFINITY0_349_OFFSET 0

#define GICD_REGS_GICD_IRM_350_LEN          1
#define GICD_REGS_GICD_IRM_350_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_350_LEN    8
#define GICD_REGS_GICD_AFFINITY2_350_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_350_LEN    8
#define GICD_REGS_GICD_AFFINITY1_350_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_350_LEN    8
#define GICD_REGS_GICD_AFFINITY0_350_OFFSET 0

#define GICD_REGS_GICD_IRM_351_LEN          1
#define GICD_REGS_GICD_IRM_351_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_351_LEN    8
#define GICD_REGS_GICD_AFFINITY2_351_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_351_LEN    8
#define GICD_REGS_GICD_AFFINITY1_351_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_351_LEN    8
#define GICD_REGS_GICD_AFFINITY0_351_OFFSET 0

#define GICD_REGS_GICD_IRM_352_LEN          1
#define GICD_REGS_GICD_IRM_352_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_352_LEN    8
#define GICD_REGS_GICD_AFFINITY2_352_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_352_LEN    8
#define GICD_REGS_GICD_AFFINITY1_352_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_352_LEN    8
#define GICD_REGS_GICD_AFFINITY0_352_OFFSET 0

#define GICD_REGS_GICD_IRM_353_LEN          1
#define GICD_REGS_GICD_IRM_353_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_353_LEN    8
#define GICD_REGS_GICD_AFFINITY2_353_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_353_LEN    8
#define GICD_REGS_GICD_AFFINITY1_353_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_353_LEN    8
#define GICD_REGS_GICD_AFFINITY0_353_OFFSET 0

#define GICD_REGS_GICD_IRM_354_LEN          1
#define GICD_REGS_GICD_IRM_354_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_354_LEN    8
#define GICD_REGS_GICD_AFFINITY2_354_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_354_LEN    8
#define GICD_REGS_GICD_AFFINITY1_354_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_354_LEN    8
#define GICD_REGS_GICD_AFFINITY0_354_OFFSET 0

#define GICD_REGS_GICD_IRM_355_LEN          1
#define GICD_REGS_GICD_IRM_355_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_355_LEN    8
#define GICD_REGS_GICD_AFFINITY2_355_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_355_LEN    8
#define GICD_REGS_GICD_AFFINITY1_355_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_355_LEN    8
#define GICD_REGS_GICD_AFFINITY0_355_OFFSET 0

#define GICD_REGS_GICD_IRM_356_LEN          1
#define GICD_REGS_GICD_IRM_356_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_356_LEN    8
#define GICD_REGS_GICD_AFFINITY2_356_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_356_LEN    8
#define GICD_REGS_GICD_AFFINITY1_356_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_356_LEN    8
#define GICD_REGS_GICD_AFFINITY0_356_OFFSET 0

#define GICD_REGS_GICD_IRM_357_LEN          1
#define GICD_REGS_GICD_IRM_357_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_357_LEN    8
#define GICD_REGS_GICD_AFFINITY2_357_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_357_LEN    8
#define GICD_REGS_GICD_AFFINITY1_357_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_357_LEN    8
#define GICD_REGS_GICD_AFFINITY0_357_OFFSET 0

#define GICD_REGS_GICD_IRM_358_LEN          1
#define GICD_REGS_GICD_IRM_358_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_358_LEN    8
#define GICD_REGS_GICD_AFFINITY2_358_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_358_LEN    8
#define GICD_REGS_GICD_AFFINITY1_358_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_358_LEN    8
#define GICD_REGS_GICD_AFFINITY0_358_OFFSET 0

#define GICD_REGS_GICD_IRM_359_LEN          1
#define GICD_REGS_GICD_IRM_359_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_359_LEN    8
#define GICD_REGS_GICD_AFFINITY2_359_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_359_LEN    8
#define GICD_REGS_GICD_AFFINITY1_359_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_359_LEN    8
#define GICD_REGS_GICD_AFFINITY0_359_OFFSET 0

#define GICD_REGS_GICD_IRM_360_LEN          1
#define GICD_REGS_GICD_IRM_360_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_360_LEN    8
#define GICD_REGS_GICD_AFFINITY2_360_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_360_LEN    8
#define GICD_REGS_GICD_AFFINITY1_360_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_360_LEN    8
#define GICD_REGS_GICD_AFFINITY0_360_OFFSET 0

#define GICD_REGS_GICD_IRM_361_LEN          1
#define GICD_REGS_GICD_IRM_361_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_361_LEN    8
#define GICD_REGS_GICD_AFFINITY2_361_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_361_LEN    8
#define GICD_REGS_GICD_AFFINITY1_361_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_361_LEN    8
#define GICD_REGS_GICD_AFFINITY0_361_OFFSET 0

#define GICD_REGS_GICD_IRM_362_LEN          1
#define GICD_REGS_GICD_IRM_362_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_362_LEN    8
#define GICD_REGS_GICD_AFFINITY2_362_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_362_LEN    8
#define GICD_REGS_GICD_AFFINITY1_362_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_362_LEN    8
#define GICD_REGS_GICD_AFFINITY0_362_OFFSET 0

#define GICD_REGS_GICD_IRM_363_LEN          1
#define GICD_REGS_GICD_IRM_363_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_363_LEN    8
#define GICD_REGS_GICD_AFFINITY2_363_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_363_LEN    8
#define GICD_REGS_GICD_AFFINITY1_363_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_363_LEN    8
#define GICD_REGS_GICD_AFFINITY0_363_OFFSET 0

#define GICD_REGS_GICD_IRM_364_LEN          1
#define GICD_REGS_GICD_IRM_364_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_364_LEN    8
#define GICD_REGS_GICD_AFFINITY2_364_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_364_LEN    8
#define GICD_REGS_GICD_AFFINITY1_364_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_364_LEN    8
#define GICD_REGS_GICD_AFFINITY0_364_OFFSET 0

#define GICD_REGS_GICD_IRM_365_LEN          1
#define GICD_REGS_GICD_IRM_365_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_365_LEN    8
#define GICD_REGS_GICD_AFFINITY2_365_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_365_LEN    8
#define GICD_REGS_GICD_AFFINITY1_365_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_365_LEN    8
#define GICD_REGS_GICD_AFFINITY0_365_OFFSET 0

#define GICD_REGS_GICD_IRM_366_LEN          1
#define GICD_REGS_GICD_IRM_366_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_366_LEN    8
#define GICD_REGS_GICD_AFFINITY2_366_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_366_LEN    8
#define GICD_REGS_GICD_AFFINITY1_366_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_366_LEN    8
#define GICD_REGS_GICD_AFFINITY0_366_OFFSET 0

#define GICD_REGS_GICD_IRM_367_LEN          1
#define GICD_REGS_GICD_IRM_367_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_367_LEN    8
#define GICD_REGS_GICD_AFFINITY2_367_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_367_LEN    8
#define GICD_REGS_GICD_AFFINITY1_367_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_367_LEN    8
#define GICD_REGS_GICD_AFFINITY0_367_OFFSET 0

#define GICD_REGS_GICD_IRM_368_LEN          1
#define GICD_REGS_GICD_IRM_368_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_368_LEN    8
#define GICD_REGS_GICD_AFFINITY2_368_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_368_LEN    8
#define GICD_REGS_GICD_AFFINITY1_368_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_368_LEN    8
#define GICD_REGS_GICD_AFFINITY0_368_OFFSET 0

#define GICD_REGS_GICD_IRM_369_LEN          1
#define GICD_REGS_GICD_IRM_369_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_369_LEN    8
#define GICD_REGS_GICD_AFFINITY2_369_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_369_LEN    8
#define GICD_REGS_GICD_AFFINITY1_369_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_369_LEN    8
#define GICD_REGS_GICD_AFFINITY0_369_OFFSET 0

#define GICD_REGS_GICD_IRM_370_LEN          1
#define GICD_REGS_GICD_IRM_370_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_370_LEN    8
#define GICD_REGS_GICD_AFFINITY2_370_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_370_LEN    8
#define GICD_REGS_GICD_AFFINITY1_370_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_370_LEN    8
#define GICD_REGS_GICD_AFFINITY0_370_OFFSET 0

#define GICD_REGS_GICD_IRM_371_LEN          1
#define GICD_REGS_GICD_IRM_371_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_371_LEN    8
#define GICD_REGS_GICD_AFFINITY2_371_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_371_LEN    8
#define GICD_REGS_GICD_AFFINITY1_371_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_371_LEN    8
#define GICD_REGS_GICD_AFFINITY0_371_OFFSET 0

#define GICD_REGS_GICD_IRM_372_LEN          1
#define GICD_REGS_GICD_IRM_372_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_372_LEN    8
#define GICD_REGS_GICD_AFFINITY2_372_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_372_LEN    8
#define GICD_REGS_GICD_AFFINITY1_372_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_372_LEN    8
#define GICD_REGS_GICD_AFFINITY0_372_OFFSET 0

#define GICD_REGS_GICD_IRM_373_LEN          1
#define GICD_REGS_GICD_IRM_373_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_373_LEN    8
#define GICD_REGS_GICD_AFFINITY2_373_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_373_LEN    8
#define GICD_REGS_GICD_AFFINITY1_373_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_373_LEN    8
#define GICD_REGS_GICD_AFFINITY0_373_OFFSET 0

#define GICD_REGS_GICD_IRM_374_LEN          1
#define GICD_REGS_GICD_IRM_374_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_374_LEN    8
#define GICD_REGS_GICD_AFFINITY2_374_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_374_LEN    8
#define GICD_REGS_GICD_AFFINITY1_374_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_374_LEN    8
#define GICD_REGS_GICD_AFFINITY0_374_OFFSET 0

#define GICD_REGS_GICD_IRM_375_LEN          1
#define GICD_REGS_GICD_IRM_375_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_375_LEN    8
#define GICD_REGS_GICD_AFFINITY2_375_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_375_LEN    8
#define GICD_REGS_GICD_AFFINITY1_375_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_375_LEN    8
#define GICD_REGS_GICD_AFFINITY0_375_OFFSET 0

#define GICD_REGS_GICD_IRM_376_LEN          1
#define GICD_REGS_GICD_IRM_376_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_376_LEN    8
#define GICD_REGS_GICD_AFFINITY2_376_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_376_LEN    8
#define GICD_REGS_GICD_AFFINITY1_376_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_376_LEN    8
#define GICD_REGS_GICD_AFFINITY0_376_OFFSET 0

#define GICD_REGS_GICD_IRM_377_LEN          1
#define GICD_REGS_GICD_IRM_377_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_377_LEN    8
#define GICD_REGS_GICD_AFFINITY2_377_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_377_LEN    8
#define GICD_REGS_GICD_AFFINITY1_377_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_377_LEN    8
#define GICD_REGS_GICD_AFFINITY0_377_OFFSET 0

#define GICD_REGS_GICD_IRM_378_LEN          1
#define GICD_REGS_GICD_IRM_378_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_378_LEN    8
#define GICD_REGS_GICD_AFFINITY2_378_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_378_LEN    8
#define GICD_REGS_GICD_AFFINITY1_378_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_378_LEN    8
#define GICD_REGS_GICD_AFFINITY0_378_OFFSET 0

#define GICD_REGS_GICD_IRM_379_LEN          1
#define GICD_REGS_GICD_IRM_379_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_379_LEN    8
#define GICD_REGS_GICD_AFFINITY2_379_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_379_LEN    8
#define GICD_REGS_GICD_AFFINITY1_379_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_379_LEN    8
#define GICD_REGS_GICD_AFFINITY0_379_OFFSET 0

#define GICD_REGS_GICD_IRM_380_LEN          1
#define GICD_REGS_GICD_IRM_380_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_380_LEN    8
#define GICD_REGS_GICD_AFFINITY2_380_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_380_LEN    8
#define GICD_REGS_GICD_AFFINITY1_380_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_380_LEN    8
#define GICD_REGS_GICD_AFFINITY0_380_OFFSET 0

#define GICD_REGS_GICD_IRM_381_LEN          1
#define GICD_REGS_GICD_IRM_381_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_381_LEN    8
#define GICD_REGS_GICD_AFFINITY2_381_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_381_LEN    8
#define GICD_REGS_GICD_AFFINITY1_381_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_381_LEN    8
#define GICD_REGS_GICD_AFFINITY0_381_OFFSET 0

#define GICD_REGS_GICD_IRM_382_LEN          1
#define GICD_REGS_GICD_IRM_382_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_382_LEN    8
#define GICD_REGS_GICD_AFFINITY2_382_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_382_LEN    8
#define GICD_REGS_GICD_AFFINITY1_382_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_382_LEN    8
#define GICD_REGS_GICD_AFFINITY0_382_OFFSET 0

#define GICD_REGS_GICD_IRM_383_LEN          1
#define GICD_REGS_GICD_IRM_383_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_383_LEN    8
#define GICD_REGS_GICD_AFFINITY2_383_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_383_LEN    8
#define GICD_REGS_GICD_AFFINITY1_383_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_383_LEN    8
#define GICD_REGS_GICD_AFFINITY0_383_OFFSET 0

#define GICD_REGS_GICD_IRM_384_LEN          1
#define GICD_REGS_GICD_IRM_384_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_384_LEN    8
#define GICD_REGS_GICD_AFFINITY2_384_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_384_LEN    8
#define GICD_REGS_GICD_AFFINITY1_384_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_384_LEN    8
#define GICD_REGS_GICD_AFFINITY0_384_OFFSET 0

#define GICD_REGS_GICD_IRM_385_LEN          1
#define GICD_REGS_GICD_IRM_385_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_385_LEN    8
#define GICD_REGS_GICD_AFFINITY2_385_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_385_LEN    8
#define GICD_REGS_GICD_AFFINITY1_385_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_385_LEN    8
#define GICD_REGS_GICD_AFFINITY0_385_OFFSET 0

#define GICD_REGS_GICD_IRM_386_LEN          1
#define GICD_REGS_GICD_IRM_386_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_386_LEN    8
#define GICD_REGS_GICD_AFFINITY2_386_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_386_LEN    8
#define GICD_REGS_GICD_AFFINITY1_386_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_386_LEN    8
#define GICD_REGS_GICD_AFFINITY0_386_OFFSET 0

#define GICD_REGS_GICD_IRM_387_LEN          1
#define GICD_REGS_GICD_IRM_387_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_387_LEN    8
#define GICD_REGS_GICD_AFFINITY2_387_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_387_LEN    8
#define GICD_REGS_GICD_AFFINITY1_387_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_387_LEN    8
#define GICD_REGS_GICD_AFFINITY0_387_OFFSET 0

#define GICD_REGS_GICD_IRM_388_LEN          1
#define GICD_REGS_GICD_IRM_388_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_388_LEN    8
#define GICD_REGS_GICD_AFFINITY2_388_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_388_LEN    8
#define GICD_REGS_GICD_AFFINITY1_388_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_388_LEN    8
#define GICD_REGS_GICD_AFFINITY0_388_OFFSET 0

#define GICD_REGS_GICD_IRM_389_LEN          1
#define GICD_REGS_GICD_IRM_389_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_389_LEN    8
#define GICD_REGS_GICD_AFFINITY2_389_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_389_LEN    8
#define GICD_REGS_GICD_AFFINITY1_389_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_389_LEN    8
#define GICD_REGS_GICD_AFFINITY0_389_OFFSET 0

#define GICD_REGS_GICD_IRM_390_LEN          1
#define GICD_REGS_GICD_IRM_390_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_390_LEN    8
#define GICD_REGS_GICD_AFFINITY2_390_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_390_LEN    8
#define GICD_REGS_GICD_AFFINITY1_390_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_390_LEN    8
#define GICD_REGS_GICD_AFFINITY0_390_OFFSET 0

#define GICD_REGS_GICD_IRM_391_LEN          1
#define GICD_REGS_GICD_IRM_391_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_391_LEN    8
#define GICD_REGS_GICD_AFFINITY2_391_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_391_LEN    8
#define GICD_REGS_GICD_AFFINITY1_391_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_391_LEN    8
#define GICD_REGS_GICD_AFFINITY0_391_OFFSET 0

#define GICD_REGS_GICD_IRM_392_LEN          1
#define GICD_REGS_GICD_IRM_392_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_392_LEN    8
#define GICD_REGS_GICD_AFFINITY2_392_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_392_LEN    8
#define GICD_REGS_GICD_AFFINITY1_392_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_392_LEN    8
#define GICD_REGS_GICD_AFFINITY0_392_OFFSET 0

#define GICD_REGS_GICD_IRM_393_LEN          1
#define GICD_REGS_GICD_IRM_393_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_393_LEN    8
#define GICD_REGS_GICD_AFFINITY2_393_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_393_LEN    8
#define GICD_REGS_GICD_AFFINITY1_393_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_393_LEN    8
#define GICD_REGS_GICD_AFFINITY0_393_OFFSET 0

#define GICD_REGS_GICD_IRM_394_LEN          1
#define GICD_REGS_GICD_IRM_394_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_394_LEN    8
#define GICD_REGS_GICD_AFFINITY2_394_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_394_LEN    8
#define GICD_REGS_GICD_AFFINITY1_394_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_394_LEN    8
#define GICD_REGS_GICD_AFFINITY0_394_OFFSET 0

#define GICD_REGS_GICD_IRM_395_LEN          1
#define GICD_REGS_GICD_IRM_395_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_395_LEN    8
#define GICD_REGS_GICD_AFFINITY2_395_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_395_LEN    8
#define GICD_REGS_GICD_AFFINITY1_395_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_395_LEN    8
#define GICD_REGS_GICD_AFFINITY0_395_OFFSET 0

#define GICD_REGS_GICD_IRM_396_LEN          1
#define GICD_REGS_GICD_IRM_396_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_396_LEN    8
#define GICD_REGS_GICD_AFFINITY2_396_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_396_LEN    8
#define GICD_REGS_GICD_AFFINITY1_396_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_396_LEN    8
#define GICD_REGS_GICD_AFFINITY0_396_OFFSET 0

#define GICD_REGS_GICD_IRM_397_LEN          1
#define GICD_REGS_GICD_IRM_397_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_397_LEN    8
#define GICD_REGS_GICD_AFFINITY2_397_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_397_LEN    8
#define GICD_REGS_GICD_AFFINITY1_397_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_397_LEN    8
#define GICD_REGS_GICD_AFFINITY0_397_OFFSET 0

#define GICD_REGS_GICD_IRM_398_LEN          1
#define GICD_REGS_GICD_IRM_398_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_398_LEN    8
#define GICD_REGS_GICD_AFFINITY2_398_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_398_LEN    8
#define GICD_REGS_GICD_AFFINITY1_398_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_398_LEN    8
#define GICD_REGS_GICD_AFFINITY0_398_OFFSET 0

#define GICD_REGS_GICD_IRM_399_LEN          1
#define GICD_REGS_GICD_IRM_399_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_399_LEN    8
#define GICD_REGS_GICD_AFFINITY2_399_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_399_LEN    8
#define GICD_REGS_GICD_AFFINITY1_399_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_399_LEN    8
#define GICD_REGS_GICD_AFFINITY0_399_OFFSET 0

#define GICD_REGS_GICD_IRM_400_LEN          1
#define GICD_REGS_GICD_IRM_400_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_400_LEN    8
#define GICD_REGS_GICD_AFFINITY2_400_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_400_LEN    8
#define GICD_REGS_GICD_AFFINITY1_400_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_400_LEN    8
#define GICD_REGS_GICD_AFFINITY0_400_OFFSET 0

#define GICD_REGS_GICD_IRM_401_LEN          1
#define GICD_REGS_GICD_IRM_401_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_401_LEN    8
#define GICD_REGS_GICD_AFFINITY2_401_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_401_LEN    8
#define GICD_REGS_GICD_AFFINITY1_401_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_401_LEN    8
#define GICD_REGS_GICD_AFFINITY0_401_OFFSET 0

#define GICD_REGS_GICD_IRM_402_LEN          1
#define GICD_REGS_GICD_IRM_402_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_402_LEN    8
#define GICD_REGS_GICD_AFFINITY2_402_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_402_LEN    8
#define GICD_REGS_GICD_AFFINITY1_402_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_402_LEN    8
#define GICD_REGS_GICD_AFFINITY0_402_OFFSET 0

#define GICD_REGS_GICD_IRM_403_LEN          1
#define GICD_REGS_GICD_IRM_403_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_403_LEN    8
#define GICD_REGS_GICD_AFFINITY2_403_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_403_LEN    8
#define GICD_REGS_GICD_AFFINITY1_403_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_403_LEN    8
#define GICD_REGS_GICD_AFFINITY0_403_OFFSET 0

#define GICD_REGS_GICD_IRM_404_LEN          1
#define GICD_REGS_GICD_IRM_404_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_404_LEN    8
#define GICD_REGS_GICD_AFFINITY2_404_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_404_LEN    8
#define GICD_REGS_GICD_AFFINITY1_404_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_404_LEN    8
#define GICD_REGS_GICD_AFFINITY0_404_OFFSET 0

#define GICD_REGS_GICD_IRM_405_LEN          1
#define GICD_REGS_GICD_IRM_405_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_405_LEN    8
#define GICD_REGS_GICD_AFFINITY2_405_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_405_LEN    8
#define GICD_REGS_GICD_AFFINITY1_405_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_405_LEN    8
#define GICD_REGS_GICD_AFFINITY0_405_OFFSET 0

#define GICD_REGS_GICD_IRM_406_LEN          1
#define GICD_REGS_GICD_IRM_406_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_406_LEN    8
#define GICD_REGS_GICD_AFFINITY2_406_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_406_LEN    8
#define GICD_REGS_GICD_AFFINITY1_406_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_406_LEN    8
#define GICD_REGS_GICD_AFFINITY0_406_OFFSET 0

#define GICD_REGS_GICD_IRM_407_LEN          1
#define GICD_REGS_GICD_IRM_407_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_407_LEN    8
#define GICD_REGS_GICD_AFFINITY2_407_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_407_LEN    8
#define GICD_REGS_GICD_AFFINITY1_407_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_407_LEN    8
#define GICD_REGS_GICD_AFFINITY0_407_OFFSET 0

#define GICD_REGS_GICD_IRM_408_LEN          1
#define GICD_REGS_GICD_IRM_408_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_408_LEN    8
#define GICD_REGS_GICD_AFFINITY2_408_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_408_LEN    8
#define GICD_REGS_GICD_AFFINITY1_408_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_408_LEN    8
#define GICD_REGS_GICD_AFFINITY0_408_OFFSET 0

#define GICD_REGS_GICD_IRM_409_LEN          1
#define GICD_REGS_GICD_IRM_409_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_409_LEN    8
#define GICD_REGS_GICD_AFFINITY2_409_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_409_LEN    8
#define GICD_REGS_GICD_AFFINITY1_409_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_409_LEN    8
#define GICD_REGS_GICD_AFFINITY0_409_OFFSET 0

#define GICD_REGS_GICD_IRM_410_LEN          1
#define GICD_REGS_GICD_IRM_410_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_410_LEN    8
#define GICD_REGS_GICD_AFFINITY2_410_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_410_LEN    8
#define GICD_REGS_GICD_AFFINITY1_410_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_410_LEN    8
#define GICD_REGS_GICD_AFFINITY0_410_OFFSET 0

#define GICD_REGS_GICD_IRM_411_LEN          1
#define GICD_REGS_GICD_IRM_411_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_411_LEN    8
#define GICD_REGS_GICD_AFFINITY2_411_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_411_LEN    8
#define GICD_REGS_GICD_AFFINITY1_411_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_411_LEN    8
#define GICD_REGS_GICD_AFFINITY0_411_OFFSET 0

#define GICD_REGS_GICD_IRM_412_LEN          1
#define GICD_REGS_GICD_IRM_412_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_412_LEN    8
#define GICD_REGS_GICD_AFFINITY2_412_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_412_LEN    8
#define GICD_REGS_GICD_AFFINITY1_412_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_412_LEN    8
#define GICD_REGS_GICD_AFFINITY0_412_OFFSET 0

#define GICD_REGS_GICD_IRM_413_LEN          1
#define GICD_REGS_GICD_IRM_413_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_413_LEN    8
#define GICD_REGS_GICD_AFFINITY2_413_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_413_LEN    8
#define GICD_REGS_GICD_AFFINITY1_413_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_413_LEN    8
#define GICD_REGS_GICD_AFFINITY0_413_OFFSET 0

#define GICD_REGS_GICD_IRM_414_LEN          1
#define GICD_REGS_GICD_IRM_414_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_414_LEN    8
#define GICD_REGS_GICD_AFFINITY2_414_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_414_LEN    8
#define GICD_REGS_GICD_AFFINITY1_414_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_414_LEN    8
#define GICD_REGS_GICD_AFFINITY0_414_OFFSET 0

#define GICD_REGS_GICD_IRM_415_LEN          1
#define GICD_REGS_GICD_IRM_415_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_415_LEN    8
#define GICD_REGS_GICD_AFFINITY2_415_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_415_LEN    8
#define GICD_REGS_GICD_AFFINITY1_415_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_415_LEN    8
#define GICD_REGS_GICD_AFFINITY0_415_OFFSET 0

#define GICD_REGS_GICD_IRM_416_LEN          1
#define GICD_REGS_GICD_IRM_416_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_416_LEN    8
#define GICD_REGS_GICD_AFFINITY2_416_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_416_LEN    8
#define GICD_REGS_GICD_AFFINITY1_416_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_416_LEN    8
#define GICD_REGS_GICD_AFFINITY0_416_OFFSET 0

#define GICD_REGS_GICD_IRM_417_LEN          1
#define GICD_REGS_GICD_IRM_417_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_417_LEN    8
#define GICD_REGS_GICD_AFFINITY2_417_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_417_LEN    8
#define GICD_REGS_GICD_AFFINITY1_417_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_417_LEN    8
#define GICD_REGS_GICD_AFFINITY0_417_OFFSET 0

#define GICD_REGS_GICD_IRM_418_LEN          1
#define GICD_REGS_GICD_IRM_418_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_418_LEN    8
#define GICD_REGS_GICD_AFFINITY2_418_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_418_LEN    8
#define GICD_REGS_GICD_AFFINITY1_418_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_418_LEN    8
#define GICD_REGS_GICD_AFFINITY0_418_OFFSET 0

#define GICD_REGS_GICD_IRM_419_LEN          1
#define GICD_REGS_GICD_IRM_419_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_419_LEN    8
#define GICD_REGS_GICD_AFFINITY2_419_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_419_LEN    8
#define GICD_REGS_GICD_AFFINITY1_419_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_419_LEN    8
#define GICD_REGS_GICD_AFFINITY0_419_OFFSET 0

#define GICD_REGS_GICD_IRM_420_LEN          1
#define GICD_REGS_GICD_IRM_420_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_420_LEN    8
#define GICD_REGS_GICD_AFFINITY2_420_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_420_LEN    8
#define GICD_REGS_GICD_AFFINITY1_420_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_420_LEN    8
#define GICD_REGS_GICD_AFFINITY0_420_OFFSET 0

#define GICD_REGS_GICD_IRM_421_LEN          1
#define GICD_REGS_GICD_IRM_421_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_421_LEN    8
#define GICD_REGS_GICD_AFFINITY2_421_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_421_LEN    8
#define GICD_REGS_GICD_AFFINITY1_421_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_421_LEN    8
#define GICD_REGS_GICD_AFFINITY0_421_OFFSET 0

#define GICD_REGS_GICD_IRM_422_LEN          1
#define GICD_REGS_GICD_IRM_422_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_422_LEN    8
#define GICD_REGS_GICD_AFFINITY2_422_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_422_LEN    8
#define GICD_REGS_GICD_AFFINITY1_422_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_422_LEN    8
#define GICD_REGS_GICD_AFFINITY0_422_OFFSET 0

#define GICD_REGS_GICD_IRM_423_LEN          1
#define GICD_REGS_GICD_IRM_423_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_423_LEN    8
#define GICD_REGS_GICD_AFFINITY2_423_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_423_LEN    8
#define GICD_REGS_GICD_AFFINITY1_423_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_423_LEN    8
#define GICD_REGS_GICD_AFFINITY0_423_OFFSET 0

#define GICD_REGS_GICD_IRM_424_LEN          1
#define GICD_REGS_GICD_IRM_424_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_424_LEN    8
#define GICD_REGS_GICD_AFFINITY2_424_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_424_LEN    8
#define GICD_REGS_GICD_AFFINITY1_424_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_424_LEN    8
#define GICD_REGS_GICD_AFFINITY0_424_OFFSET 0

#define GICD_REGS_GICD_IRM_425_LEN          1
#define GICD_REGS_GICD_IRM_425_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_425_LEN    8
#define GICD_REGS_GICD_AFFINITY2_425_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_425_LEN    8
#define GICD_REGS_GICD_AFFINITY1_425_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_425_LEN    8
#define GICD_REGS_GICD_AFFINITY0_425_OFFSET 0

#define GICD_REGS_GICD_IRM_426_LEN          1
#define GICD_REGS_GICD_IRM_426_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_426_LEN    8
#define GICD_REGS_GICD_AFFINITY2_426_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_426_LEN    8
#define GICD_REGS_GICD_AFFINITY1_426_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_426_LEN    8
#define GICD_REGS_GICD_AFFINITY0_426_OFFSET 0

#define GICD_REGS_GICD_IRM_427_LEN          1
#define GICD_REGS_GICD_IRM_427_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_427_LEN    8
#define GICD_REGS_GICD_AFFINITY2_427_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_427_LEN    8
#define GICD_REGS_GICD_AFFINITY1_427_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_427_LEN    8
#define GICD_REGS_GICD_AFFINITY0_427_OFFSET 0

#define GICD_REGS_GICD_IRM_428_LEN          1
#define GICD_REGS_GICD_IRM_428_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_428_LEN    8
#define GICD_REGS_GICD_AFFINITY2_428_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_428_LEN    8
#define GICD_REGS_GICD_AFFINITY1_428_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_428_LEN    8
#define GICD_REGS_GICD_AFFINITY0_428_OFFSET 0

#define GICD_REGS_GICD_IRM_429_LEN          1
#define GICD_REGS_GICD_IRM_429_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_429_LEN    8
#define GICD_REGS_GICD_AFFINITY2_429_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_429_LEN    8
#define GICD_REGS_GICD_AFFINITY1_429_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_429_LEN    8
#define GICD_REGS_GICD_AFFINITY0_429_OFFSET 0

#define GICD_REGS_GICD_IRM_430_LEN          1
#define GICD_REGS_GICD_IRM_430_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_430_LEN    8
#define GICD_REGS_GICD_AFFINITY2_430_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_430_LEN    8
#define GICD_REGS_GICD_AFFINITY1_430_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_430_LEN    8
#define GICD_REGS_GICD_AFFINITY0_430_OFFSET 0

#define GICD_REGS_GICD_IRM_431_LEN          1
#define GICD_REGS_GICD_IRM_431_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_431_LEN    8
#define GICD_REGS_GICD_AFFINITY2_431_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_431_LEN    8
#define GICD_REGS_GICD_AFFINITY1_431_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_431_LEN    8
#define GICD_REGS_GICD_AFFINITY0_431_OFFSET 0

#define GICD_REGS_GICD_IRM_432_LEN          1
#define GICD_REGS_GICD_IRM_432_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_432_LEN    8
#define GICD_REGS_GICD_AFFINITY2_432_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_432_LEN    8
#define GICD_REGS_GICD_AFFINITY1_432_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_432_LEN    8
#define GICD_REGS_GICD_AFFINITY0_432_OFFSET 0

#define GICD_REGS_GICD_IRM_433_LEN          1
#define GICD_REGS_GICD_IRM_433_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_433_LEN    8
#define GICD_REGS_GICD_AFFINITY2_433_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_433_LEN    8
#define GICD_REGS_GICD_AFFINITY1_433_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_433_LEN    8
#define GICD_REGS_GICD_AFFINITY0_433_OFFSET 0

#define GICD_REGS_GICD_IRM_434_LEN          1
#define GICD_REGS_GICD_IRM_434_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_434_LEN    8
#define GICD_REGS_GICD_AFFINITY2_434_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_434_LEN    8
#define GICD_REGS_GICD_AFFINITY1_434_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_434_LEN    8
#define GICD_REGS_GICD_AFFINITY0_434_OFFSET 0

#define GICD_REGS_GICD_IRM_435_LEN          1
#define GICD_REGS_GICD_IRM_435_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_435_LEN    8
#define GICD_REGS_GICD_AFFINITY2_435_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_435_LEN    8
#define GICD_REGS_GICD_AFFINITY1_435_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_435_LEN    8
#define GICD_REGS_GICD_AFFINITY0_435_OFFSET 0

#define GICD_REGS_GICD_IRM_436_LEN          1
#define GICD_REGS_GICD_IRM_436_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_436_LEN    8
#define GICD_REGS_GICD_AFFINITY2_436_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_436_LEN    8
#define GICD_REGS_GICD_AFFINITY1_436_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_436_LEN    8
#define GICD_REGS_GICD_AFFINITY0_436_OFFSET 0

#define GICD_REGS_GICD_IRM_437_LEN          1
#define GICD_REGS_GICD_IRM_437_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_437_LEN    8
#define GICD_REGS_GICD_AFFINITY2_437_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_437_LEN    8
#define GICD_REGS_GICD_AFFINITY1_437_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_437_LEN    8
#define GICD_REGS_GICD_AFFINITY0_437_OFFSET 0

#define GICD_REGS_GICD_IRM_438_LEN          1
#define GICD_REGS_GICD_IRM_438_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_438_LEN    8
#define GICD_REGS_GICD_AFFINITY2_438_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_438_LEN    8
#define GICD_REGS_GICD_AFFINITY1_438_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_438_LEN    8
#define GICD_REGS_GICD_AFFINITY0_438_OFFSET 0

#define GICD_REGS_GICD_IRM_439_LEN          1
#define GICD_REGS_GICD_IRM_439_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_439_LEN    8
#define GICD_REGS_GICD_AFFINITY2_439_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_439_LEN    8
#define GICD_REGS_GICD_AFFINITY1_439_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_439_LEN    8
#define GICD_REGS_GICD_AFFINITY0_439_OFFSET 0

#define GICD_REGS_GICD_IRM_440_LEN          1
#define GICD_REGS_GICD_IRM_440_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_440_LEN    8
#define GICD_REGS_GICD_AFFINITY2_440_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_440_LEN    8
#define GICD_REGS_GICD_AFFINITY1_440_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_440_LEN    8
#define GICD_REGS_GICD_AFFINITY0_440_OFFSET 0

#define GICD_REGS_GICD_IRM_441_LEN          1
#define GICD_REGS_GICD_IRM_441_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_441_LEN    8
#define GICD_REGS_GICD_AFFINITY2_441_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_441_LEN    8
#define GICD_REGS_GICD_AFFINITY1_441_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_441_LEN    8
#define GICD_REGS_GICD_AFFINITY0_441_OFFSET 0

#define GICD_REGS_GICD_IRM_442_LEN          1
#define GICD_REGS_GICD_IRM_442_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_442_LEN    8
#define GICD_REGS_GICD_AFFINITY2_442_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_442_LEN    8
#define GICD_REGS_GICD_AFFINITY1_442_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_442_LEN    8
#define GICD_REGS_GICD_AFFINITY0_442_OFFSET 0

#define GICD_REGS_GICD_IRM_443_LEN          1
#define GICD_REGS_GICD_IRM_443_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_443_LEN    8
#define GICD_REGS_GICD_AFFINITY2_443_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_443_LEN    8
#define GICD_REGS_GICD_AFFINITY1_443_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_443_LEN    8
#define GICD_REGS_GICD_AFFINITY0_443_OFFSET 0

#define GICD_REGS_GICD_IRM_444_LEN          1
#define GICD_REGS_GICD_IRM_444_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_444_LEN    8
#define GICD_REGS_GICD_AFFINITY2_444_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_444_LEN    8
#define GICD_REGS_GICD_AFFINITY1_444_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_444_LEN    8
#define GICD_REGS_GICD_AFFINITY0_444_OFFSET 0

#define GICD_REGS_GICD_IRM_445_LEN          1
#define GICD_REGS_GICD_IRM_445_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_445_LEN    8
#define GICD_REGS_GICD_AFFINITY2_445_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_445_LEN    8
#define GICD_REGS_GICD_AFFINITY1_445_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_445_LEN    8
#define GICD_REGS_GICD_AFFINITY0_445_OFFSET 0

#define GICD_REGS_GICD_IRM_446_LEN          1
#define GICD_REGS_GICD_IRM_446_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_446_LEN    8
#define GICD_REGS_GICD_AFFINITY2_446_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_446_LEN    8
#define GICD_REGS_GICD_AFFINITY1_446_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_446_LEN    8
#define GICD_REGS_GICD_AFFINITY0_446_OFFSET 0

#define GICD_REGS_GICD_IRM_447_LEN          1
#define GICD_REGS_GICD_IRM_447_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_447_LEN    8
#define GICD_REGS_GICD_AFFINITY2_447_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_447_LEN    8
#define GICD_REGS_GICD_AFFINITY1_447_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_447_LEN    8
#define GICD_REGS_GICD_AFFINITY0_447_OFFSET 0

#define GICD_REGS_GICD_IRM_448_LEN          1
#define GICD_REGS_GICD_IRM_448_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_448_LEN    8
#define GICD_REGS_GICD_AFFINITY2_448_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_448_LEN    8
#define GICD_REGS_GICD_AFFINITY1_448_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_448_LEN    8
#define GICD_REGS_GICD_AFFINITY0_448_OFFSET 0

#define GICD_REGS_GICD_IRM_449_LEN          1
#define GICD_REGS_GICD_IRM_449_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_449_LEN    8
#define GICD_REGS_GICD_AFFINITY2_449_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_449_LEN    8
#define GICD_REGS_GICD_AFFINITY1_449_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_449_LEN    8
#define GICD_REGS_GICD_AFFINITY0_449_OFFSET 0

#define GICD_REGS_GICD_IRM_450_LEN          1
#define GICD_REGS_GICD_IRM_450_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_450_LEN    8
#define GICD_REGS_GICD_AFFINITY2_450_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_450_LEN    8
#define GICD_REGS_GICD_AFFINITY1_450_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_450_LEN    8
#define GICD_REGS_GICD_AFFINITY0_450_OFFSET 0

#define GICD_REGS_GICD_IRM_451_LEN          1
#define GICD_REGS_GICD_IRM_451_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_451_LEN    8
#define GICD_REGS_GICD_AFFINITY2_451_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_451_LEN    8
#define GICD_REGS_GICD_AFFINITY1_451_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_451_LEN    8
#define GICD_REGS_GICD_AFFINITY0_451_OFFSET 0

#define GICD_REGS_GICD_IRM_452_LEN          1
#define GICD_REGS_GICD_IRM_452_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_452_LEN    8
#define GICD_REGS_GICD_AFFINITY2_452_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_452_LEN    8
#define GICD_REGS_GICD_AFFINITY1_452_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_452_LEN    8
#define GICD_REGS_GICD_AFFINITY0_452_OFFSET 0

#define GICD_REGS_GICD_IRM_453_LEN          1
#define GICD_REGS_GICD_IRM_453_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_453_LEN    8
#define GICD_REGS_GICD_AFFINITY2_453_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_453_LEN    8
#define GICD_REGS_GICD_AFFINITY1_453_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_453_LEN    8
#define GICD_REGS_GICD_AFFINITY0_453_OFFSET 0

#define GICD_REGS_GICD_IRM_454_LEN          1
#define GICD_REGS_GICD_IRM_454_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_454_LEN    8
#define GICD_REGS_GICD_AFFINITY2_454_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_454_LEN    8
#define GICD_REGS_GICD_AFFINITY1_454_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_454_LEN    8
#define GICD_REGS_GICD_AFFINITY0_454_OFFSET 0

#define GICD_REGS_GICD_IRM_455_LEN          1
#define GICD_REGS_GICD_IRM_455_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_455_LEN    8
#define GICD_REGS_GICD_AFFINITY2_455_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_455_LEN    8
#define GICD_REGS_GICD_AFFINITY1_455_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_455_LEN    8
#define GICD_REGS_GICD_AFFINITY0_455_OFFSET 0

#define GICD_REGS_GICD_IRM_456_LEN          1
#define GICD_REGS_GICD_IRM_456_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_456_LEN    8
#define GICD_REGS_GICD_AFFINITY2_456_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_456_LEN    8
#define GICD_REGS_GICD_AFFINITY1_456_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_456_LEN    8
#define GICD_REGS_GICD_AFFINITY0_456_OFFSET 0

#define GICD_REGS_GICD_IRM_457_LEN          1
#define GICD_REGS_GICD_IRM_457_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_457_LEN    8
#define GICD_REGS_GICD_AFFINITY2_457_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_457_LEN    8
#define GICD_REGS_GICD_AFFINITY1_457_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_457_LEN    8
#define GICD_REGS_GICD_AFFINITY0_457_OFFSET 0

#define GICD_REGS_GICD_IRM_458_LEN          1
#define GICD_REGS_GICD_IRM_458_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_458_LEN    8
#define GICD_REGS_GICD_AFFINITY2_458_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_458_LEN    8
#define GICD_REGS_GICD_AFFINITY1_458_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_458_LEN    8
#define GICD_REGS_GICD_AFFINITY0_458_OFFSET 0

#define GICD_REGS_GICD_IRM_459_LEN          1
#define GICD_REGS_GICD_IRM_459_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_459_LEN    8
#define GICD_REGS_GICD_AFFINITY2_459_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_459_LEN    8
#define GICD_REGS_GICD_AFFINITY1_459_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_459_LEN    8
#define GICD_REGS_GICD_AFFINITY0_459_OFFSET 0

#define GICD_REGS_GICD_IRM_460_LEN          1
#define GICD_REGS_GICD_IRM_460_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_460_LEN    8
#define GICD_REGS_GICD_AFFINITY2_460_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_460_LEN    8
#define GICD_REGS_GICD_AFFINITY1_460_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_460_LEN    8
#define GICD_REGS_GICD_AFFINITY0_460_OFFSET 0

#define GICD_REGS_GICD_IRM_461_LEN          1
#define GICD_REGS_GICD_IRM_461_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_461_LEN    8
#define GICD_REGS_GICD_AFFINITY2_461_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_461_LEN    8
#define GICD_REGS_GICD_AFFINITY1_461_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_461_LEN    8
#define GICD_REGS_GICD_AFFINITY0_461_OFFSET 0

#define GICD_REGS_GICD_IRM_462_LEN          1
#define GICD_REGS_GICD_IRM_462_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_462_LEN    8
#define GICD_REGS_GICD_AFFINITY2_462_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_462_LEN    8
#define GICD_REGS_GICD_AFFINITY1_462_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_462_LEN    8
#define GICD_REGS_GICD_AFFINITY0_462_OFFSET 0

#define GICD_REGS_GICD_IRM_463_LEN          1
#define GICD_REGS_GICD_IRM_463_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_463_LEN    8
#define GICD_REGS_GICD_AFFINITY2_463_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_463_LEN    8
#define GICD_REGS_GICD_AFFINITY1_463_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_463_LEN    8
#define GICD_REGS_GICD_AFFINITY0_463_OFFSET 0

#define GICD_REGS_GICD_IRM_464_LEN          1
#define GICD_REGS_GICD_IRM_464_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_464_LEN    8
#define GICD_REGS_GICD_AFFINITY2_464_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_464_LEN    8
#define GICD_REGS_GICD_AFFINITY1_464_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_464_LEN    8
#define GICD_REGS_GICD_AFFINITY0_464_OFFSET 0

#define GICD_REGS_GICD_IRM_465_LEN          1
#define GICD_REGS_GICD_IRM_465_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_465_LEN    8
#define GICD_REGS_GICD_AFFINITY2_465_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_465_LEN    8
#define GICD_REGS_GICD_AFFINITY1_465_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_465_LEN    8
#define GICD_REGS_GICD_AFFINITY0_465_OFFSET 0

#define GICD_REGS_GICD_IRM_466_LEN          1
#define GICD_REGS_GICD_IRM_466_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_466_LEN    8
#define GICD_REGS_GICD_AFFINITY2_466_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_466_LEN    8
#define GICD_REGS_GICD_AFFINITY1_466_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_466_LEN    8
#define GICD_REGS_GICD_AFFINITY0_466_OFFSET 0

#define GICD_REGS_GICD_IRM_467_LEN          1
#define GICD_REGS_GICD_IRM_467_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_467_LEN    8
#define GICD_REGS_GICD_AFFINITY2_467_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_467_LEN    8
#define GICD_REGS_GICD_AFFINITY1_467_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_467_LEN    8
#define GICD_REGS_GICD_AFFINITY0_467_OFFSET 0

#define GICD_REGS_GICD_IRM_468_LEN          1
#define GICD_REGS_GICD_IRM_468_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_468_LEN    8
#define GICD_REGS_GICD_AFFINITY2_468_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_468_LEN    8
#define GICD_REGS_GICD_AFFINITY1_468_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_468_LEN    8
#define GICD_REGS_GICD_AFFINITY0_468_OFFSET 0

#define GICD_REGS_GICD_IRM_469_LEN          1
#define GICD_REGS_GICD_IRM_469_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_469_LEN    8
#define GICD_REGS_GICD_AFFINITY2_469_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_469_LEN    8
#define GICD_REGS_GICD_AFFINITY1_469_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_469_LEN    8
#define GICD_REGS_GICD_AFFINITY0_469_OFFSET 0

#define GICD_REGS_GICD_IRM_470_LEN          1
#define GICD_REGS_GICD_IRM_470_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_470_LEN    8
#define GICD_REGS_GICD_AFFINITY2_470_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_470_LEN    8
#define GICD_REGS_GICD_AFFINITY1_470_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_470_LEN    8
#define GICD_REGS_GICD_AFFINITY0_470_OFFSET 0

#define GICD_REGS_GICD_IRM_471_LEN          1
#define GICD_REGS_GICD_IRM_471_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_471_LEN    8
#define GICD_REGS_GICD_AFFINITY2_471_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_471_LEN    8
#define GICD_REGS_GICD_AFFINITY1_471_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_471_LEN    8
#define GICD_REGS_GICD_AFFINITY0_471_OFFSET 0

#define GICD_REGS_GICD_IRM_472_LEN          1
#define GICD_REGS_GICD_IRM_472_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_472_LEN    8
#define GICD_REGS_GICD_AFFINITY2_472_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_472_LEN    8
#define GICD_REGS_GICD_AFFINITY1_472_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_472_LEN    8
#define GICD_REGS_GICD_AFFINITY0_472_OFFSET 0

#define GICD_REGS_GICD_IRM_473_LEN          1
#define GICD_REGS_GICD_IRM_473_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_473_LEN    8
#define GICD_REGS_GICD_AFFINITY2_473_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_473_LEN    8
#define GICD_REGS_GICD_AFFINITY1_473_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_473_LEN    8
#define GICD_REGS_GICD_AFFINITY0_473_OFFSET 0

#define GICD_REGS_GICD_IRM_474_LEN          1
#define GICD_REGS_GICD_IRM_474_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_474_LEN    8
#define GICD_REGS_GICD_AFFINITY2_474_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_474_LEN    8
#define GICD_REGS_GICD_AFFINITY1_474_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_474_LEN    8
#define GICD_REGS_GICD_AFFINITY0_474_OFFSET 0

#define GICD_REGS_GICD_IRM_475_LEN          1
#define GICD_REGS_GICD_IRM_475_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_475_LEN    8
#define GICD_REGS_GICD_AFFINITY2_475_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_475_LEN    8
#define GICD_REGS_GICD_AFFINITY1_475_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_475_LEN    8
#define GICD_REGS_GICD_AFFINITY0_475_OFFSET 0

#define GICD_REGS_GICD_IRM_476_LEN          1
#define GICD_REGS_GICD_IRM_476_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_476_LEN    8
#define GICD_REGS_GICD_AFFINITY2_476_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_476_LEN    8
#define GICD_REGS_GICD_AFFINITY1_476_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_476_LEN    8
#define GICD_REGS_GICD_AFFINITY0_476_OFFSET 0

#define GICD_REGS_GICD_IRM_477_LEN          1
#define GICD_REGS_GICD_IRM_477_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_477_LEN    8
#define GICD_REGS_GICD_AFFINITY2_477_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_477_LEN    8
#define GICD_REGS_GICD_AFFINITY1_477_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_477_LEN    8
#define GICD_REGS_GICD_AFFINITY0_477_OFFSET 0

#define GICD_REGS_GICD_IRM_478_LEN          1
#define GICD_REGS_GICD_IRM_478_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_478_LEN    8
#define GICD_REGS_GICD_AFFINITY2_478_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_478_LEN    8
#define GICD_REGS_GICD_AFFINITY1_478_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_478_LEN    8
#define GICD_REGS_GICD_AFFINITY0_478_OFFSET 0

#define GICD_REGS_GICD_IRM_479_LEN          1
#define GICD_REGS_GICD_IRM_479_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_479_LEN    8
#define GICD_REGS_GICD_AFFINITY2_479_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_479_LEN    8
#define GICD_REGS_GICD_AFFINITY1_479_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_479_LEN    8
#define GICD_REGS_GICD_AFFINITY0_479_OFFSET 0

#define GICD_REGS_GICD_IRM_480_LEN          1
#define GICD_REGS_GICD_IRM_480_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_480_LEN    8
#define GICD_REGS_GICD_AFFINITY2_480_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_480_LEN    8
#define GICD_REGS_GICD_AFFINITY1_480_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_480_LEN    8
#define GICD_REGS_GICD_AFFINITY0_480_OFFSET 0

#define GICD_REGS_GICD_IRM_481_LEN          1
#define GICD_REGS_GICD_IRM_481_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_481_LEN    8
#define GICD_REGS_GICD_AFFINITY2_481_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_481_LEN    8
#define GICD_REGS_GICD_AFFINITY1_481_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_481_LEN    8
#define GICD_REGS_GICD_AFFINITY0_481_OFFSET 0

#define GICD_REGS_GICD_IRM_482_LEN          1
#define GICD_REGS_GICD_IRM_482_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_482_LEN    8
#define GICD_REGS_GICD_AFFINITY2_482_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_482_LEN    8
#define GICD_REGS_GICD_AFFINITY1_482_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_482_LEN    8
#define GICD_REGS_GICD_AFFINITY0_482_OFFSET 0

#define GICD_REGS_GICD_IRM_483_LEN          1
#define GICD_REGS_GICD_IRM_483_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_483_LEN    8
#define GICD_REGS_GICD_AFFINITY2_483_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_483_LEN    8
#define GICD_REGS_GICD_AFFINITY1_483_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_483_LEN    8
#define GICD_REGS_GICD_AFFINITY0_483_OFFSET 0

#define GICD_REGS_GICD_IRM_484_LEN          1
#define GICD_REGS_GICD_IRM_484_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_484_LEN    8
#define GICD_REGS_GICD_AFFINITY2_484_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_484_LEN    8
#define GICD_REGS_GICD_AFFINITY1_484_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_484_LEN    8
#define GICD_REGS_GICD_AFFINITY0_484_OFFSET 0

#define GICD_REGS_GICD_IRM_485_LEN          1
#define GICD_REGS_GICD_IRM_485_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_485_LEN    8
#define GICD_REGS_GICD_AFFINITY2_485_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_485_LEN    8
#define GICD_REGS_GICD_AFFINITY1_485_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_485_LEN    8
#define GICD_REGS_GICD_AFFINITY0_485_OFFSET 0

#define GICD_REGS_GICD_IRM_486_LEN          1
#define GICD_REGS_GICD_IRM_486_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_486_LEN    8
#define GICD_REGS_GICD_AFFINITY2_486_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_486_LEN    8
#define GICD_REGS_GICD_AFFINITY1_486_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_486_LEN    8
#define GICD_REGS_GICD_AFFINITY0_486_OFFSET 0

#define GICD_REGS_GICD_IRM_487_LEN          1
#define GICD_REGS_GICD_IRM_487_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_487_LEN    8
#define GICD_REGS_GICD_AFFINITY2_487_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_487_LEN    8
#define GICD_REGS_GICD_AFFINITY1_487_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_487_LEN    8
#define GICD_REGS_GICD_AFFINITY0_487_OFFSET 0

#define GICD_REGS_GICD_IRM_488_LEN          1
#define GICD_REGS_GICD_IRM_488_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_488_LEN    8
#define GICD_REGS_GICD_AFFINITY2_488_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_488_LEN    8
#define GICD_REGS_GICD_AFFINITY1_488_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_488_LEN    8
#define GICD_REGS_GICD_AFFINITY0_488_OFFSET 0

#define GICD_REGS_GICD_IRM_489_LEN          1
#define GICD_REGS_GICD_IRM_489_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_489_LEN    8
#define GICD_REGS_GICD_AFFINITY2_489_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_489_LEN    8
#define GICD_REGS_GICD_AFFINITY1_489_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_489_LEN    8
#define GICD_REGS_GICD_AFFINITY0_489_OFFSET 0

#define GICD_REGS_GICD_IRM_490_LEN          1
#define GICD_REGS_GICD_IRM_490_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_490_LEN    8
#define GICD_REGS_GICD_AFFINITY2_490_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_490_LEN    8
#define GICD_REGS_GICD_AFFINITY1_490_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_490_LEN    8
#define GICD_REGS_GICD_AFFINITY0_490_OFFSET 0

#define GICD_REGS_GICD_IRM_491_LEN          1
#define GICD_REGS_GICD_IRM_491_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_491_LEN    8
#define GICD_REGS_GICD_AFFINITY2_491_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_491_LEN    8
#define GICD_REGS_GICD_AFFINITY1_491_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_491_LEN    8
#define GICD_REGS_GICD_AFFINITY0_491_OFFSET 0

#define GICD_REGS_GICD_IRM_492_LEN          1
#define GICD_REGS_GICD_IRM_492_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_492_LEN    8
#define GICD_REGS_GICD_AFFINITY2_492_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_492_LEN    8
#define GICD_REGS_GICD_AFFINITY1_492_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_492_LEN    8
#define GICD_REGS_GICD_AFFINITY0_492_OFFSET 0

#define GICD_REGS_GICD_IRM_493_LEN          1
#define GICD_REGS_GICD_IRM_493_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_493_LEN    8
#define GICD_REGS_GICD_AFFINITY2_493_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_493_LEN    8
#define GICD_REGS_GICD_AFFINITY1_493_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_493_LEN    8
#define GICD_REGS_GICD_AFFINITY0_493_OFFSET 0

#define GICD_REGS_GICD_IRM_494_LEN          1
#define GICD_REGS_GICD_IRM_494_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_494_LEN    8
#define GICD_REGS_GICD_AFFINITY2_494_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_494_LEN    8
#define GICD_REGS_GICD_AFFINITY1_494_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_494_LEN    8
#define GICD_REGS_GICD_AFFINITY0_494_OFFSET 0

#define GICD_REGS_GICD_IRM_495_LEN          1
#define GICD_REGS_GICD_IRM_495_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_495_LEN    8
#define GICD_REGS_GICD_AFFINITY2_495_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_495_LEN    8
#define GICD_REGS_GICD_AFFINITY1_495_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_495_LEN    8
#define GICD_REGS_GICD_AFFINITY0_495_OFFSET 0

#define GICD_REGS_GICD_IRM_496_LEN          1
#define GICD_REGS_GICD_IRM_496_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_496_LEN    8
#define GICD_REGS_GICD_AFFINITY2_496_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_496_LEN    8
#define GICD_REGS_GICD_AFFINITY1_496_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_496_LEN    8
#define GICD_REGS_GICD_AFFINITY0_496_OFFSET 0

#define GICD_REGS_GICD_IRM_497_LEN          1
#define GICD_REGS_GICD_IRM_497_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_497_LEN    8
#define GICD_REGS_GICD_AFFINITY2_497_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_497_LEN    8
#define GICD_REGS_GICD_AFFINITY1_497_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_497_LEN    8
#define GICD_REGS_GICD_AFFINITY0_497_OFFSET 0

#define GICD_REGS_GICD_IRM_498_LEN          1
#define GICD_REGS_GICD_IRM_498_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_498_LEN    8
#define GICD_REGS_GICD_AFFINITY2_498_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_498_LEN    8
#define GICD_REGS_GICD_AFFINITY1_498_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_498_LEN    8
#define GICD_REGS_GICD_AFFINITY0_498_OFFSET 0

#define GICD_REGS_GICD_IRM_499_LEN          1
#define GICD_REGS_GICD_IRM_499_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_499_LEN    8
#define GICD_REGS_GICD_AFFINITY2_499_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_499_LEN    8
#define GICD_REGS_GICD_AFFINITY1_499_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_499_LEN    8
#define GICD_REGS_GICD_AFFINITY0_499_OFFSET 0

#define GICD_REGS_GICD_IRM_500_LEN          1
#define GICD_REGS_GICD_IRM_500_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_500_LEN    8
#define GICD_REGS_GICD_AFFINITY2_500_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_500_LEN    8
#define GICD_REGS_GICD_AFFINITY1_500_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_500_LEN    8
#define GICD_REGS_GICD_AFFINITY0_500_OFFSET 0

#define GICD_REGS_GICD_IRM_501_LEN          1
#define GICD_REGS_GICD_IRM_501_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_501_LEN    8
#define GICD_REGS_GICD_AFFINITY2_501_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_501_LEN    8
#define GICD_REGS_GICD_AFFINITY1_501_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_501_LEN    8
#define GICD_REGS_GICD_AFFINITY0_501_OFFSET 0

#define GICD_REGS_GICD_IRM_502_LEN          1
#define GICD_REGS_GICD_IRM_502_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_502_LEN    8
#define GICD_REGS_GICD_AFFINITY2_502_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_502_LEN    8
#define GICD_REGS_GICD_AFFINITY1_502_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_502_LEN    8
#define GICD_REGS_GICD_AFFINITY0_502_OFFSET 0

#define GICD_REGS_GICD_IRM_503_LEN          1
#define GICD_REGS_GICD_IRM_503_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_503_LEN    8
#define GICD_REGS_GICD_AFFINITY2_503_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_503_LEN    8
#define GICD_REGS_GICD_AFFINITY1_503_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_503_LEN    8
#define GICD_REGS_GICD_AFFINITY0_503_OFFSET 0

#define GICD_REGS_GICD_IRM_504_LEN          1
#define GICD_REGS_GICD_IRM_504_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_504_LEN    8
#define GICD_REGS_GICD_AFFINITY2_504_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_504_LEN    8
#define GICD_REGS_GICD_AFFINITY1_504_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_504_LEN    8
#define GICD_REGS_GICD_AFFINITY0_504_OFFSET 0

#define GICD_REGS_GICD_IRM_505_LEN          1
#define GICD_REGS_GICD_IRM_505_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_505_LEN    8
#define GICD_REGS_GICD_AFFINITY2_505_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_505_LEN    8
#define GICD_REGS_GICD_AFFINITY1_505_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_505_LEN    8
#define GICD_REGS_GICD_AFFINITY0_505_OFFSET 0

#define GICD_REGS_GICD_IRM_506_LEN          1
#define GICD_REGS_GICD_IRM_506_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_506_LEN    8
#define GICD_REGS_GICD_AFFINITY2_506_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_506_LEN    8
#define GICD_REGS_GICD_AFFINITY1_506_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_506_LEN    8
#define GICD_REGS_GICD_AFFINITY0_506_OFFSET 0

#define GICD_REGS_GICD_IRM_507_LEN          1
#define GICD_REGS_GICD_IRM_507_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_507_LEN    8
#define GICD_REGS_GICD_AFFINITY2_507_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_507_LEN    8
#define GICD_REGS_GICD_AFFINITY1_507_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_507_LEN    8
#define GICD_REGS_GICD_AFFINITY0_507_OFFSET 0

#define GICD_REGS_GICD_IRM_508_LEN          1
#define GICD_REGS_GICD_IRM_508_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_508_LEN    8
#define GICD_REGS_GICD_AFFINITY2_508_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_508_LEN    8
#define GICD_REGS_GICD_AFFINITY1_508_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_508_LEN    8
#define GICD_REGS_GICD_AFFINITY0_508_OFFSET 0

#define GICD_REGS_GICD_IRM_509_LEN          1
#define GICD_REGS_GICD_IRM_509_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_509_LEN    8
#define GICD_REGS_GICD_AFFINITY2_509_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_509_LEN    8
#define GICD_REGS_GICD_AFFINITY1_509_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_509_LEN    8
#define GICD_REGS_GICD_AFFINITY0_509_OFFSET 0

#define GICD_REGS_GICD_IRM_510_LEN          1
#define GICD_REGS_GICD_IRM_510_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_510_LEN    8
#define GICD_REGS_GICD_AFFINITY2_510_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_510_LEN    8
#define GICD_REGS_GICD_AFFINITY1_510_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_510_LEN    8
#define GICD_REGS_GICD_AFFINITY0_510_OFFSET 0

#define GICD_REGS_GICD_IRM_511_LEN          1
#define GICD_REGS_GICD_IRM_511_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_511_LEN    8
#define GICD_REGS_GICD_AFFINITY2_511_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_511_LEN    8
#define GICD_REGS_GICD_AFFINITY1_511_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_511_LEN    8
#define GICD_REGS_GICD_AFFINITY0_511_OFFSET 0

#define GICD_REGS_GICD_IRM_512_LEN          1
#define GICD_REGS_GICD_IRM_512_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_512_LEN    8
#define GICD_REGS_GICD_AFFINITY2_512_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_512_LEN    8
#define GICD_REGS_GICD_AFFINITY1_512_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_512_LEN    8
#define GICD_REGS_GICD_AFFINITY0_512_OFFSET 0

#define GICD_REGS_GICD_IRM_513_LEN          1
#define GICD_REGS_GICD_IRM_513_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_513_LEN    8
#define GICD_REGS_GICD_AFFINITY2_513_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_513_LEN    8
#define GICD_REGS_GICD_AFFINITY1_513_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_513_LEN    8
#define GICD_REGS_GICD_AFFINITY0_513_OFFSET 0

#define GICD_REGS_GICD_IRM_514_LEN          1
#define GICD_REGS_GICD_IRM_514_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_514_LEN    8
#define GICD_REGS_GICD_AFFINITY2_514_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_514_LEN    8
#define GICD_REGS_GICD_AFFINITY1_514_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_514_LEN    8
#define GICD_REGS_GICD_AFFINITY0_514_OFFSET 0

#define GICD_REGS_GICD_IRM_515_LEN          1
#define GICD_REGS_GICD_IRM_515_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_515_LEN    8
#define GICD_REGS_GICD_AFFINITY2_515_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_515_LEN    8
#define GICD_REGS_GICD_AFFINITY1_515_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_515_LEN    8
#define GICD_REGS_GICD_AFFINITY0_515_OFFSET 0

#define GICD_REGS_GICD_IRM_516_LEN          1
#define GICD_REGS_GICD_IRM_516_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_516_LEN    8
#define GICD_REGS_GICD_AFFINITY2_516_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_516_LEN    8
#define GICD_REGS_GICD_AFFINITY1_516_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_516_LEN    8
#define GICD_REGS_GICD_AFFINITY0_516_OFFSET 0

#define GICD_REGS_GICD_IRM_517_LEN          1
#define GICD_REGS_GICD_IRM_517_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_517_LEN    8
#define GICD_REGS_GICD_AFFINITY2_517_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_517_LEN    8
#define GICD_REGS_GICD_AFFINITY1_517_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_517_LEN    8
#define GICD_REGS_GICD_AFFINITY0_517_OFFSET 0

#define GICD_REGS_GICD_IRM_518_LEN          1
#define GICD_REGS_GICD_IRM_518_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_518_LEN    8
#define GICD_REGS_GICD_AFFINITY2_518_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_518_LEN    8
#define GICD_REGS_GICD_AFFINITY1_518_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_518_LEN    8
#define GICD_REGS_GICD_AFFINITY0_518_OFFSET 0

#define GICD_REGS_GICD_IRM_519_LEN          1
#define GICD_REGS_GICD_IRM_519_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_519_LEN    8
#define GICD_REGS_GICD_AFFINITY2_519_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_519_LEN    8
#define GICD_REGS_GICD_AFFINITY1_519_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_519_LEN    8
#define GICD_REGS_GICD_AFFINITY0_519_OFFSET 0

#define GICD_REGS_GICD_IRM_520_LEN          1
#define GICD_REGS_GICD_IRM_520_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_520_LEN    8
#define GICD_REGS_GICD_AFFINITY2_520_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_520_LEN    8
#define GICD_REGS_GICD_AFFINITY1_520_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_520_LEN    8
#define GICD_REGS_GICD_AFFINITY0_520_OFFSET 0

#define GICD_REGS_GICD_IRM_521_LEN          1
#define GICD_REGS_GICD_IRM_521_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_521_LEN    8
#define GICD_REGS_GICD_AFFINITY2_521_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_521_LEN    8
#define GICD_REGS_GICD_AFFINITY1_521_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_521_LEN    8
#define GICD_REGS_GICD_AFFINITY0_521_OFFSET 0

#define GICD_REGS_GICD_IRM_522_LEN          1
#define GICD_REGS_GICD_IRM_522_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_522_LEN    8
#define GICD_REGS_GICD_AFFINITY2_522_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_522_LEN    8
#define GICD_REGS_GICD_AFFINITY1_522_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_522_LEN    8
#define GICD_REGS_GICD_AFFINITY0_522_OFFSET 0

#define GICD_REGS_GICD_IRM_523_LEN          1
#define GICD_REGS_GICD_IRM_523_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_523_LEN    8
#define GICD_REGS_GICD_AFFINITY2_523_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_523_LEN    8
#define GICD_REGS_GICD_AFFINITY1_523_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_523_LEN    8
#define GICD_REGS_GICD_AFFINITY0_523_OFFSET 0

#define GICD_REGS_GICD_IRM_524_LEN          1
#define GICD_REGS_GICD_IRM_524_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_524_LEN    8
#define GICD_REGS_GICD_AFFINITY2_524_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_524_LEN    8
#define GICD_REGS_GICD_AFFINITY1_524_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_524_LEN    8
#define GICD_REGS_GICD_AFFINITY0_524_OFFSET 0

#define GICD_REGS_GICD_IRM_525_LEN          1
#define GICD_REGS_GICD_IRM_525_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_525_LEN    8
#define GICD_REGS_GICD_AFFINITY2_525_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_525_LEN    8
#define GICD_REGS_GICD_AFFINITY1_525_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_525_LEN    8
#define GICD_REGS_GICD_AFFINITY0_525_OFFSET 0

#define GICD_REGS_GICD_IRM_526_LEN          1
#define GICD_REGS_GICD_IRM_526_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_526_LEN    8
#define GICD_REGS_GICD_AFFINITY2_526_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_526_LEN    8
#define GICD_REGS_GICD_AFFINITY1_526_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_526_LEN    8
#define GICD_REGS_GICD_AFFINITY0_526_OFFSET 0

#define GICD_REGS_GICD_IRM_527_LEN          1
#define GICD_REGS_GICD_IRM_527_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_527_LEN    8
#define GICD_REGS_GICD_AFFINITY2_527_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_527_LEN    8
#define GICD_REGS_GICD_AFFINITY1_527_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_527_LEN    8
#define GICD_REGS_GICD_AFFINITY0_527_OFFSET 0

#define GICD_REGS_GICD_IRM_528_LEN          1
#define GICD_REGS_GICD_IRM_528_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_528_LEN    8
#define GICD_REGS_GICD_AFFINITY2_528_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_528_LEN    8
#define GICD_REGS_GICD_AFFINITY1_528_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_528_LEN    8
#define GICD_REGS_GICD_AFFINITY0_528_OFFSET 0

#define GICD_REGS_GICD_IRM_529_LEN          1
#define GICD_REGS_GICD_IRM_529_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_529_LEN    8
#define GICD_REGS_GICD_AFFINITY2_529_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_529_LEN    8
#define GICD_REGS_GICD_AFFINITY1_529_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_529_LEN    8
#define GICD_REGS_GICD_AFFINITY0_529_OFFSET 0

#define GICD_REGS_GICD_IRM_530_LEN          1
#define GICD_REGS_GICD_IRM_530_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_530_LEN    8
#define GICD_REGS_GICD_AFFINITY2_530_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_530_LEN    8
#define GICD_REGS_GICD_AFFINITY1_530_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_530_LEN    8
#define GICD_REGS_GICD_AFFINITY0_530_OFFSET 0

#define GICD_REGS_GICD_IRM_531_LEN          1
#define GICD_REGS_GICD_IRM_531_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_531_LEN    8
#define GICD_REGS_GICD_AFFINITY2_531_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_531_LEN    8
#define GICD_REGS_GICD_AFFINITY1_531_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_531_LEN    8
#define GICD_REGS_GICD_AFFINITY0_531_OFFSET 0

#define GICD_REGS_GICD_IRM_532_LEN          1
#define GICD_REGS_GICD_IRM_532_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_532_LEN    8
#define GICD_REGS_GICD_AFFINITY2_532_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_532_LEN    8
#define GICD_REGS_GICD_AFFINITY1_532_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_532_LEN    8
#define GICD_REGS_GICD_AFFINITY0_532_OFFSET 0

#define GICD_REGS_GICD_IRM_533_LEN          1
#define GICD_REGS_GICD_IRM_533_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_533_LEN    8
#define GICD_REGS_GICD_AFFINITY2_533_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_533_LEN    8
#define GICD_REGS_GICD_AFFINITY1_533_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_533_LEN    8
#define GICD_REGS_GICD_AFFINITY0_533_OFFSET 0

#define GICD_REGS_GICD_IRM_534_LEN          1
#define GICD_REGS_GICD_IRM_534_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_534_LEN    8
#define GICD_REGS_GICD_AFFINITY2_534_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_534_LEN    8
#define GICD_REGS_GICD_AFFINITY1_534_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_534_LEN    8
#define GICD_REGS_GICD_AFFINITY0_534_OFFSET 0

#define GICD_REGS_GICD_IRM_535_LEN          1
#define GICD_REGS_GICD_IRM_535_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_535_LEN    8
#define GICD_REGS_GICD_AFFINITY2_535_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_535_LEN    8
#define GICD_REGS_GICD_AFFINITY1_535_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_535_LEN    8
#define GICD_REGS_GICD_AFFINITY0_535_OFFSET 0

#define GICD_REGS_GICD_IRM_536_LEN          1
#define GICD_REGS_GICD_IRM_536_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_536_LEN    8
#define GICD_REGS_GICD_AFFINITY2_536_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_536_LEN    8
#define GICD_REGS_GICD_AFFINITY1_536_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_536_LEN    8
#define GICD_REGS_GICD_AFFINITY0_536_OFFSET 0

#define GICD_REGS_GICD_IRM_537_LEN          1
#define GICD_REGS_GICD_IRM_537_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_537_LEN    8
#define GICD_REGS_GICD_AFFINITY2_537_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_537_LEN    8
#define GICD_REGS_GICD_AFFINITY1_537_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_537_LEN    8
#define GICD_REGS_GICD_AFFINITY0_537_OFFSET 0

#define GICD_REGS_GICD_IRM_538_LEN          1
#define GICD_REGS_GICD_IRM_538_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_538_LEN    8
#define GICD_REGS_GICD_AFFINITY2_538_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_538_LEN    8
#define GICD_REGS_GICD_AFFINITY1_538_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_538_LEN    8
#define GICD_REGS_GICD_AFFINITY0_538_OFFSET 0

#define GICD_REGS_GICD_IRM_539_LEN          1
#define GICD_REGS_GICD_IRM_539_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_539_LEN    8
#define GICD_REGS_GICD_AFFINITY2_539_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_539_LEN    8
#define GICD_REGS_GICD_AFFINITY1_539_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_539_LEN    8
#define GICD_REGS_GICD_AFFINITY0_539_OFFSET 0

#define GICD_REGS_GICD_IRM_540_LEN          1
#define GICD_REGS_GICD_IRM_540_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_540_LEN    8
#define GICD_REGS_GICD_AFFINITY2_540_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_540_LEN    8
#define GICD_REGS_GICD_AFFINITY1_540_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_540_LEN    8
#define GICD_REGS_GICD_AFFINITY0_540_OFFSET 0

#define GICD_REGS_GICD_IRM_541_LEN          1
#define GICD_REGS_GICD_IRM_541_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_541_LEN    8
#define GICD_REGS_GICD_AFFINITY2_541_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_541_LEN    8
#define GICD_REGS_GICD_AFFINITY1_541_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_541_LEN    8
#define GICD_REGS_GICD_AFFINITY0_541_OFFSET 0

#define GICD_REGS_GICD_IRM_542_LEN          1
#define GICD_REGS_GICD_IRM_542_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_542_LEN    8
#define GICD_REGS_GICD_AFFINITY2_542_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_542_LEN    8
#define GICD_REGS_GICD_AFFINITY1_542_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_542_LEN    8
#define GICD_REGS_GICD_AFFINITY0_542_OFFSET 0

#define GICD_REGS_GICD_IRM_543_LEN          1
#define GICD_REGS_GICD_IRM_543_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_543_LEN    8
#define GICD_REGS_GICD_AFFINITY2_543_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_543_LEN    8
#define GICD_REGS_GICD_AFFINITY1_543_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_543_LEN    8
#define GICD_REGS_GICD_AFFINITY0_543_OFFSET 0

#define GICD_REGS_GICD_IRM_544_LEN          1
#define GICD_REGS_GICD_IRM_544_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_544_LEN    8
#define GICD_REGS_GICD_AFFINITY2_544_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_544_LEN    8
#define GICD_REGS_GICD_AFFINITY1_544_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_544_LEN    8
#define GICD_REGS_GICD_AFFINITY0_544_OFFSET 0

#define GICD_REGS_GICD_IRM_545_LEN          1
#define GICD_REGS_GICD_IRM_545_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_545_LEN    8
#define GICD_REGS_GICD_AFFINITY2_545_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_545_LEN    8
#define GICD_REGS_GICD_AFFINITY1_545_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_545_LEN    8
#define GICD_REGS_GICD_AFFINITY0_545_OFFSET 0

#define GICD_REGS_GICD_IRM_546_LEN          1
#define GICD_REGS_GICD_IRM_546_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_546_LEN    8
#define GICD_REGS_GICD_AFFINITY2_546_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_546_LEN    8
#define GICD_REGS_GICD_AFFINITY1_546_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_546_LEN    8
#define GICD_REGS_GICD_AFFINITY0_546_OFFSET 0

#define GICD_REGS_GICD_IRM_547_LEN          1
#define GICD_REGS_GICD_IRM_547_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_547_LEN    8
#define GICD_REGS_GICD_AFFINITY2_547_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_547_LEN    8
#define GICD_REGS_GICD_AFFINITY1_547_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_547_LEN    8
#define GICD_REGS_GICD_AFFINITY0_547_OFFSET 0

#define GICD_REGS_GICD_IRM_548_LEN          1
#define GICD_REGS_GICD_IRM_548_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_548_LEN    8
#define GICD_REGS_GICD_AFFINITY2_548_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_548_LEN    8
#define GICD_REGS_GICD_AFFINITY1_548_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_548_LEN    8
#define GICD_REGS_GICD_AFFINITY0_548_OFFSET 0

#define GICD_REGS_GICD_IRM_549_LEN          1
#define GICD_REGS_GICD_IRM_549_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_549_LEN    8
#define GICD_REGS_GICD_AFFINITY2_549_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_549_LEN    8
#define GICD_REGS_GICD_AFFINITY1_549_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_549_LEN    8
#define GICD_REGS_GICD_AFFINITY0_549_OFFSET 0

#define GICD_REGS_GICD_IRM_550_LEN          1
#define GICD_REGS_GICD_IRM_550_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_550_LEN    8
#define GICD_REGS_GICD_AFFINITY2_550_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_550_LEN    8
#define GICD_REGS_GICD_AFFINITY1_550_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_550_LEN    8
#define GICD_REGS_GICD_AFFINITY0_550_OFFSET 0

#define GICD_REGS_GICD_IRM_551_LEN          1
#define GICD_REGS_GICD_IRM_551_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_551_LEN    8
#define GICD_REGS_GICD_AFFINITY2_551_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_551_LEN    8
#define GICD_REGS_GICD_AFFINITY1_551_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_551_LEN    8
#define GICD_REGS_GICD_AFFINITY0_551_OFFSET 0

#define GICD_REGS_GICD_IRM_552_LEN          1
#define GICD_REGS_GICD_IRM_552_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_552_LEN    8
#define GICD_REGS_GICD_AFFINITY2_552_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_552_LEN    8
#define GICD_REGS_GICD_AFFINITY1_552_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_552_LEN    8
#define GICD_REGS_GICD_AFFINITY0_552_OFFSET 0

#define GICD_REGS_GICD_IRM_553_LEN          1
#define GICD_REGS_GICD_IRM_553_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_553_LEN    8
#define GICD_REGS_GICD_AFFINITY2_553_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_553_LEN    8
#define GICD_REGS_GICD_AFFINITY1_553_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_553_LEN    8
#define GICD_REGS_GICD_AFFINITY0_553_OFFSET 0

#define GICD_REGS_GICD_IRM_554_LEN          1
#define GICD_REGS_GICD_IRM_554_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_554_LEN    8
#define GICD_REGS_GICD_AFFINITY2_554_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_554_LEN    8
#define GICD_REGS_GICD_AFFINITY1_554_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_554_LEN    8
#define GICD_REGS_GICD_AFFINITY0_554_OFFSET 0

#define GICD_REGS_GICD_IRM_555_LEN          1
#define GICD_REGS_GICD_IRM_555_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_555_LEN    8
#define GICD_REGS_GICD_AFFINITY2_555_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_555_LEN    8
#define GICD_REGS_GICD_AFFINITY1_555_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_555_LEN    8
#define GICD_REGS_GICD_AFFINITY0_555_OFFSET 0

#define GICD_REGS_GICD_IRM_556_LEN          1
#define GICD_REGS_GICD_IRM_556_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_556_LEN    8
#define GICD_REGS_GICD_AFFINITY2_556_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_556_LEN    8
#define GICD_REGS_GICD_AFFINITY1_556_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_556_LEN    8
#define GICD_REGS_GICD_AFFINITY0_556_OFFSET 0

#define GICD_REGS_GICD_IRM_557_LEN          1
#define GICD_REGS_GICD_IRM_557_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_557_LEN    8
#define GICD_REGS_GICD_AFFINITY2_557_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_557_LEN    8
#define GICD_REGS_GICD_AFFINITY1_557_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_557_LEN    8
#define GICD_REGS_GICD_AFFINITY0_557_OFFSET 0

#define GICD_REGS_GICD_IRM_558_LEN          1
#define GICD_REGS_GICD_IRM_558_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_558_LEN    8
#define GICD_REGS_GICD_AFFINITY2_558_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_558_LEN    8
#define GICD_REGS_GICD_AFFINITY1_558_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_558_LEN    8
#define GICD_REGS_GICD_AFFINITY0_558_OFFSET 0

#define GICD_REGS_GICD_IRM_559_LEN          1
#define GICD_REGS_GICD_IRM_559_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_559_LEN    8
#define GICD_REGS_GICD_AFFINITY2_559_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_559_LEN    8
#define GICD_REGS_GICD_AFFINITY1_559_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_559_LEN    8
#define GICD_REGS_GICD_AFFINITY0_559_OFFSET 0

#define GICD_REGS_GICD_IRM_560_LEN          1
#define GICD_REGS_GICD_IRM_560_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_560_LEN    8
#define GICD_REGS_GICD_AFFINITY2_560_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_560_LEN    8
#define GICD_REGS_GICD_AFFINITY1_560_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_560_LEN    8
#define GICD_REGS_GICD_AFFINITY0_560_OFFSET 0

#define GICD_REGS_GICD_IRM_561_LEN          1
#define GICD_REGS_GICD_IRM_561_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_561_LEN    8
#define GICD_REGS_GICD_AFFINITY2_561_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_561_LEN    8
#define GICD_REGS_GICD_AFFINITY1_561_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_561_LEN    8
#define GICD_REGS_GICD_AFFINITY0_561_OFFSET 0

#define GICD_REGS_GICD_IRM_562_LEN          1
#define GICD_REGS_GICD_IRM_562_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_562_LEN    8
#define GICD_REGS_GICD_AFFINITY2_562_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_562_LEN    8
#define GICD_REGS_GICD_AFFINITY1_562_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_562_LEN    8
#define GICD_REGS_GICD_AFFINITY0_562_OFFSET 0

#define GICD_REGS_GICD_IRM_563_LEN          1
#define GICD_REGS_GICD_IRM_563_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_563_LEN    8
#define GICD_REGS_GICD_AFFINITY2_563_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_563_LEN    8
#define GICD_REGS_GICD_AFFINITY1_563_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_563_LEN    8
#define GICD_REGS_GICD_AFFINITY0_563_OFFSET 0

#define GICD_REGS_GICD_IRM_564_LEN          1
#define GICD_REGS_GICD_IRM_564_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_564_LEN    8
#define GICD_REGS_GICD_AFFINITY2_564_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_564_LEN    8
#define GICD_REGS_GICD_AFFINITY1_564_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_564_LEN    8
#define GICD_REGS_GICD_AFFINITY0_564_OFFSET 0

#define GICD_REGS_GICD_IRM_565_LEN          1
#define GICD_REGS_GICD_IRM_565_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_565_LEN    8
#define GICD_REGS_GICD_AFFINITY2_565_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_565_LEN    8
#define GICD_REGS_GICD_AFFINITY1_565_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_565_LEN    8
#define GICD_REGS_GICD_AFFINITY0_565_OFFSET 0

#define GICD_REGS_GICD_IRM_566_LEN          1
#define GICD_REGS_GICD_IRM_566_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_566_LEN    8
#define GICD_REGS_GICD_AFFINITY2_566_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_566_LEN    8
#define GICD_REGS_GICD_AFFINITY1_566_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_566_LEN    8
#define GICD_REGS_GICD_AFFINITY0_566_OFFSET 0

#define GICD_REGS_GICD_IRM_567_LEN          1
#define GICD_REGS_GICD_IRM_567_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_567_LEN    8
#define GICD_REGS_GICD_AFFINITY2_567_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_567_LEN    8
#define GICD_REGS_GICD_AFFINITY1_567_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_567_LEN    8
#define GICD_REGS_GICD_AFFINITY0_567_OFFSET 0

#define GICD_REGS_GICD_IRM_568_LEN          1
#define GICD_REGS_GICD_IRM_568_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_568_LEN    8
#define GICD_REGS_GICD_AFFINITY2_568_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_568_LEN    8
#define GICD_REGS_GICD_AFFINITY1_568_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_568_LEN    8
#define GICD_REGS_GICD_AFFINITY0_568_OFFSET 0

#define GICD_REGS_GICD_IRM_569_LEN          1
#define GICD_REGS_GICD_IRM_569_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_569_LEN    8
#define GICD_REGS_GICD_AFFINITY2_569_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_569_LEN    8
#define GICD_REGS_GICD_AFFINITY1_569_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_569_LEN    8
#define GICD_REGS_GICD_AFFINITY0_569_OFFSET 0

#define GICD_REGS_GICD_IRM_570_LEN          1
#define GICD_REGS_GICD_IRM_570_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_570_LEN    8
#define GICD_REGS_GICD_AFFINITY2_570_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_570_LEN    8
#define GICD_REGS_GICD_AFFINITY1_570_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_570_LEN    8
#define GICD_REGS_GICD_AFFINITY0_570_OFFSET 0

#define GICD_REGS_GICD_IRM_571_LEN          1
#define GICD_REGS_GICD_IRM_571_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_571_LEN    8
#define GICD_REGS_GICD_AFFINITY2_571_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_571_LEN    8
#define GICD_REGS_GICD_AFFINITY1_571_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_571_LEN    8
#define GICD_REGS_GICD_AFFINITY0_571_OFFSET 0

#define GICD_REGS_GICD_IRM_572_LEN          1
#define GICD_REGS_GICD_IRM_572_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_572_LEN    8
#define GICD_REGS_GICD_AFFINITY2_572_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_572_LEN    8
#define GICD_REGS_GICD_AFFINITY1_572_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_572_LEN    8
#define GICD_REGS_GICD_AFFINITY0_572_OFFSET 0

#define GICD_REGS_GICD_IRM_573_LEN          1
#define GICD_REGS_GICD_IRM_573_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_573_LEN    8
#define GICD_REGS_GICD_AFFINITY2_573_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_573_LEN    8
#define GICD_REGS_GICD_AFFINITY1_573_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_573_LEN    8
#define GICD_REGS_GICD_AFFINITY0_573_OFFSET 0

#define GICD_REGS_GICD_IRM_574_LEN          1
#define GICD_REGS_GICD_IRM_574_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_574_LEN    8
#define GICD_REGS_GICD_AFFINITY2_574_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_574_LEN    8
#define GICD_REGS_GICD_AFFINITY1_574_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_574_LEN    8
#define GICD_REGS_GICD_AFFINITY0_574_OFFSET 0

#define GICD_REGS_GICD_IRM_575_LEN          1
#define GICD_REGS_GICD_IRM_575_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_575_LEN    8
#define GICD_REGS_GICD_AFFINITY2_575_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_575_LEN    8
#define GICD_REGS_GICD_AFFINITY1_575_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_575_LEN    8
#define GICD_REGS_GICD_AFFINITY0_575_OFFSET 0

#define GICD_REGS_GICD_IRM_576_LEN          1
#define GICD_REGS_GICD_IRM_576_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_576_LEN    8
#define GICD_REGS_GICD_AFFINITY2_576_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_576_LEN    8
#define GICD_REGS_GICD_AFFINITY1_576_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_576_LEN    8
#define GICD_REGS_GICD_AFFINITY0_576_OFFSET 0

#define GICD_REGS_GICD_IRM_577_LEN          1
#define GICD_REGS_GICD_IRM_577_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_577_LEN    8
#define GICD_REGS_GICD_AFFINITY2_577_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_577_LEN    8
#define GICD_REGS_GICD_AFFINITY1_577_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_577_LEN    8
#define GICD_REGS_GICD_AFFINITY0_577_OFFSET 0

#define GICD_REGS_GICD_IRM_578_LEN          1
#define GICD_REGS_GICD_IRM_578_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_578_LEN    8
#define GICD_REGS_GICD_AFFINITY2_578_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_578_LEN    8
#define GICD_REGS_GICD_AFFINITY1_578_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_578_LEN    8
#define GICD_REGS_GICD_AFFINITY0_578_OFFSET 0

#define GICD_REGS_GICD_IRM_579_LEN          1
#define GICD_REGS_GICD_IRM_579_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_579_LEN    8
#define GICD_REGS_GICD_AFFINITY2_579_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_579_LEN    8
#define GICD_REGS_GICD_AFFINITY1_579_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_579_LEN    8
#define GICD_REGS_GICD_AFFINITY0_579_OFFSET 0

#define GICD_REGS_GICD_IRM_580_LEN          1
#define GICD_REGS_GICD_IRM_580_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_580_LEN    8
#define GICD_REGS_GICD_AFFINITY2_580_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_580_LEN    8
#define GICD_REGS_GICD_AFFINITY1_580_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_580_LEN    8
#define GICD_REGS_GICD_AFFINITY0_580_OFFSET 0

#define GICD_REGS_GICD_IRM_581_LEN          1
#define GICD_REGS_GICD_IRM_581_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_581_LEN    8
#define GICD_REGS_GICD_AFFINITY2_581_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_581_LEN    8
#define GICD_REGS_GICD_AFFINITY1_581_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_581_LEN    8
#define GICD_REGS_GICD_AFFINITY0_581_OFFSET 0

#define GICD_REGS_GICD_IRM_582_LEN          1
#define GICD_REGS_GICD_IRM_582_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_582_LEN    8
#define GICD_REGS_GICD_AFFINITY2_582_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_582_LEN    8
#define GICD_REGS_GICD_AFFINITY1_582_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_582_LEN    8
#define GICD_REGS_GICD_AFFINITY0_582_OFFSET 0

#define GICD_REGS_GICD_IRM_583_LEN          1
#define GICD_REGS_GICD_IRM_583_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_583_LEN    8
#define GICD_REGS_GICD_AFFINITY2_583_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_583_LEN    8
#define GICD_REGS_GICD_AFFINITY1_583_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_583_LEN    8
#define GICD_REGS_GICD_AFFINITY0_583_OFFSET 0

#define GICD_REGS_GICD_IRM_584_LEN          1
#define GICD_REGS_GICD_IRM_584_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_584_LEN    8
#define GICD_REGS_GICD_AFFINITY2_584_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_584_LEN    8
#define GICD_REGS_GICD_AFFINITY1_584_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_584_LEN    8
#define GICD_REGS_GICD_AFFINITY0_584_OFFSET 0

#define GICD_REGS_GICD_IRM_585_LEN          1
#define GICD_REGS_GICD_IRM_585_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_585_LEN    8
#define GICD_REGS_GICD_AFFINITY2_585_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_585_LEN    8
#define GICD_REGS_GICD_AFFINITY1_585_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_585_LEN    8
#define GICD_REGS_GICD_AFFINITY0_585_OFFSET 0

#define GICD_REGS_GICD_IRM_586_LEN          1
#define GICD_REGS_GICD_IRM_586_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_586_LEN    8
#define GICD_REGS_GICD_AFFINITY2_586_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_586_LEN    8
#define GICD_REGS_GICD_AFFINITY1_586_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_586_LEN    8
#define GICD_REGS_GICD_AFFINITY0_586_OFFSET 0

#define GICD_REGS_GICD_IRM_587_LEN          1
#define GICD_REGS_GICD_IRM_587_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_587_LEN    8
#define GICD_REGS_GICD_AFFINITY2_587_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_587_LEN    8
#define GICD_REGS_GICD_AFFINITY1_587_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_587_LEN    8
#define GICD_REGS_GICD_AFFINITY0_587_OFFSET 0

#define GICD_REGS_GICD_IRM_588_LEN          1
#define GICD_REGS_GICD_IRM_588_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_588_LEN    8
#define GICD_REGS_GICD_AFFINITY2_588_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_588_LEN    8
#define GICD_REGS_GICD_AFFINITY1_588_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_588_LEN    8
#define GICD_REGS_GICD_AFFINITY0_588_OFFSET 0

#define GICD_REGS_GICD_IRM_589_LEN          1
#define GICD_REGS_GICD_IRM_589_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_589_LEN    8
#define GICD_REGS_GICD_AFFINITY2_589_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_589_LEN    8
#define GICD_REGS_GICD_AFFINITY1_589_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_589_LEN    8
#define GICD_REGS_GICD_AFFINITY0_589_OFFSET 0

#define GICD_REGS_GICD_IRM_590_LEN          1
#define GICD_REGS_GICD_IRM_590_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_590_LEN    8
#define GICD_REGS_GICD_AFFINITY2_590_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_590_LEN    8
#define GICD_REGS_GICD_AFFINITY1_590_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_590_LEN    8
#define GICD_REGS_GICD_AFFINITY0_590_OFFSET 0

#define GICD_REGS_GICD_IRM_591_LEN          1
#define GICD_REGS_GICD_IRM_591_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_591_LEN    8
#define GICD_REGS_GICD_AFFINITY2_591_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_591_LEN    8
#define GICD_REGS_GICD_AFFINITY1_591_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_591_LEN    8
#define GICD_REGS_GICD_AFFINITY0_591_OFFSET 0

#define GICD_REGS_GICD_IRM_592_LEN          1
#define GICD_REGS_GICD_IRM_592_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_592_LEN    8
#define GICD_REGS_GICD_AFFINITY2_592_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_592_LEN    8
#define GICD_REGS_GICD_AFFINITY1_592_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_592_LEN    8
#define GICD_REGS_GICD_AFFINITY0_592_OFFSET 0

#define GICD_REGS_GICD_IRM_593_LEN          1
#define GICD_REGS_GICD_IRM_593_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_593_LEN    8
#define GICD_REGS_GICD_AFFINITY2_593_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_593_LEN    8
#define GICD_REGS_GICD_AFFINITY1_593_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_593_LEN    8
#define GICD_REGS_GICD_AFFINITY0_593_OFFSET 0

#define GICD_REGS_GICD_IRM_594_LEN          1
#define GICD_REGS_GICD_IRM_594_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_594_LEN    8
#define GICD_REGS_GICD_AFFINITY2_594_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_594_LEN    8
#define GICD_REGS_GICD_AFFINITY1_594_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_594_LEN    8
#define GICD_REGS_GICD_AFFINITY0_594_OFFSET 0

#define GICD_REGS_GICD_IRM_595_LEN          1
#define GICD_REGS_GICD_IRM_595_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_595_LEN    8
#define GICD_REGS_GICD_AFFINITY2_595_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_595_LEN    8
#define GICD_REGS_GICD_AFFINITY1_595_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_595_LEN    8
#define GICD_REGS_GICD_AFFINITY0_595_OFFSET 0

#define GICD_REGS_GICD_IRM_596_LEN          1
#define GICD_REGS_GICD_IRM_596_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_596_LEN    8
#define GICD_REGS_GICD_AFFINITY2_596_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_596_LEN    8
#define GICD_REGS_GICD_AFFINITY1_596_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_596_LEN    8
#define GICD_REGS_GICD_AFFINITY0_596_OFFSET 0

#define GICD_REGS_GICD_IRM_597_LEN          1
#define GICD_REGS_GICD_IRM_597_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_597_LEN    8
#define GICD_REGS_GICD_AFFINITY2_597_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_597_LEN    8
#define GICD_REGS_GICD_AFFINITY1_597_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_597_LEN    8
#define GICD_REGS_GICD_AFFINITY0_597_OFFSET 0

#define GICD_REGS_GICD_IRM_598_LEN          1
#define GICD_REGS_GICD_IRM_598_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_598_LEN    8
#define GICD_REGS_GICD_AFFINITY2_598_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_598_LEN    8
#define GICD_REGS_GICD_AFFINITY1_598_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_598_LEN    8
#define GICD_REGS_GICD_AFFINITY0_598_OFFSET 0

#define GICD_REGS_GICD_IRM_599_LEN          1
#define GICD_REGS_GICD_IRM_599_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_599_LEN    8
#define GICD_REGS_GICD_AFFINITY2_599_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_599_LEN    8
#define GICD_REGS_GICD_AFFINITY1_599_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_599_LEN    8
#define GICD_REGS_GICD_AFFINITY0_599_OFFSET 0

#define GICD_REGS_GICD_IRM_600_LEN          1
#define GICD_REGS_GICD_IRM_600_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_600_LEN    8
#define GICD_REGS_GICD_AFFINITY2_600_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_600_LEN    8
#define GICD_REGS_GICD_AFFINITY1_600_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_600_LEN    8
#define GICD_REGS_GICD_AFFINITY0_600_OFFSET 0

#define GICD_REGS_GICD_IRM_601_LEN          1
#define GICD_REGS_GICD_IRM_601_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_601_LEN    8
#define GICD_REGS_GICD_AFFINITY2_601_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_601_LEN    8
#define GICD_REGS_GICD_AFFINITY1_601_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_601_LEN    8
#define GICD_REGS_GICD_AFFINITY0_601_OFFSET 0

#define GICD_REGS_GICD_IRM_602_LEN          1
#define GICD_REGS_GICD_IRM_602_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_602_LEN    8
#define GICD_REGS_GICD_AFFINITY2_602_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_602_LEN    8
#define GICD_REGS_GICD_AFFINITY1_602_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_602_LEN    8
#define GICD_REGS_GICD_AFFINITY0_602_OFFSET 0

#define GICD_REGS_GICD_IRM_603_LEN          1
#define GICD_REGS_GICD_IRM_603_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_603_LEN    8
#define GICD_REGS_GICD_AFFINITY2_603_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_603_LEN    8
#define GICD_REGS_GICD_AFFINITY1_603_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_603_LEN    8
#define GICD_REGS_GICD_AFFINITY0_603_OFFSET 0

#define GICD_REGS_GICD_IRM_604_LEN          1
#define GICD_REGS_GICD_IRM_604_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_604_LEN    8
#define GICD_REGS_GICD_AFFINITY2_604_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_604_LEN    8
#define GICD_REGS_GICD_AFFINITY1_604_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_604_LEN    8
#define GICD_REGS_GICD_AFFINITY0_604_OFFSET 0

#define GICD_REGS_GICD_IRM_605_LEN          1
#define GICD_REGS_GICD_IRM_605_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_605_LEN    8
#define GICD_REGS_GICD_AFFINITY2_605_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_605_LEN    8
#define GICD_REGS_GICD_AFFINITY1_605_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_605_LEN    8
#define GICD_REGS_GICD_AFFINITY0_605_OFFSET 0

#define GICD_REGS_GICD_IRM_606_LEN          1
#define GICD_REGS_GICD_IRM_606_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_606_LEN    8
#define GICD_REGS_GICD_AFFINITY2_606_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_606_LEN    8
#define GICD_REGS_GICD_AFFINITY1_606_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_606_LEN    8
#define GICD_REGS_GICD_AFFINITY0_606_OFFSET 0

#define GICD_REGS_GICD_IRM_607_LEN          1
#define GICD_REGS_GICD_IRM_607_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_607_LEN    8
#define GICD_REGS_GICD_AFFINITY2_607_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_607_LEN    8
#define GICD_REGS_GICD_AFFINITY1_607_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_607_LEN    8
#define GICD_REGS_GICD_AFFINITY0_607_OFFSET 0

#define GICD_REGS_GICD_IRM_608_LEN          1
#define GICD_REGS_GICD_IRM_608_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_608_LEN    8
#define GICD_REGS_GICD_AFFINITY2_608_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_608_LEN    8
#define GICD_REGS_GICD_AFFINITY1_608_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_608_LEN    8
#define GICD_REGS_GICD_AFFINITY0_608_OFFSET 0

#define GICD_REGS_GICD_IRM_609_LEN          1
#define GICD_REGS_GICD_IRM_609_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_609_LEN    8
#define GICD_REGS_GICD_AFFINITY2_609_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_609_LEN    8
#define GICD_REGS_GICD_AFFINITY1_609_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_609_LEN    8
#define GICD_REGS_GICD_AFFINITY0_609_OFFSET 0

#define GICD_REGS_GICD_IRM_610_LEN          1
#define GICD_REGS_GICD_IRM_610_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_610_LEN    8
#define GICD_REGS_GICD_AFFINITY2_610_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_610_LEN    8
#define GICD_REGS_GICD_AFFINITY1_610_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_610_LEN    8
#define GICD_REGS_GICD_AFFINITY0_610_OFFSET 0

#define GICD_REGS_GICD_IRM_611_LEN          1
#define GICD_REGS_GICD_IRM_611_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_611_LEN    8
#define GICD_REGS_GICD_AFFINITY2_611_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_611_LEN    8
#define GICD_REGS_GICD_AFFINITY1_611_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_611_LEN    8
#define GICD_REGS_GICD_AFFINITY0_611_OFFSET 0

#define GICD_REGS_GICD_IRM_612_LEN          1
#define GICD_REGS_GICD_IRM_612_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_612_LEN    8
#define GICD_REGS_GICD_AFFINITY2_612_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_612_LEN    8
#define GICD_REGS_GICD_AFFINITY1_612_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_612_LEN    8
#define GICD_REGS_GICD_AFFINITY0_612_OFFSET 0

#define GICD_REGS_GICD_IRM_613_LEN          1
#define GICD_REGS_GICD_IRM_613_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_613_LEN    8
#define GICD_REGS_GICD_AFFINITY2_613_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_613_LEN    8
#define GICD_REGS_GICD_AFFINITY1_613_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_613_LEN    8
#define GICD_REGS_GICD_AFFINITY0_613_OFFSET 0

#define GICD_REGS_GICD_IRM_614_LEN          1
#define GICD_REGS_GICD_IRM_614_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_614_LEN    8
#define GICD_REGS_GICD_AFFINITY2_614_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_614_LEN    8
#define GICD_REGS_GICD_AFFINITY1_614_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_614_LEN    8
#define GICD_REGS_GICD_AFFINITY0_614_OFFSET 0

#define GICD_REGS_GICD_IRM_615_LEN          1
#define GICD_REGS_GICD_IRM_615_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_615_LEN    8
#define GICD_REGS_GICD_AFFINITY2_615_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_615_LEN    8
#define GICD_REGS_GICD_AFFINITY1_615_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_615_LEN    8
#define GICD_REGS_GICD_AFFINITY0_615_OFFSET 0

#define GICD_REGS_GICD_IRM_616_LEN          1
#define GICD_REGS_GICD_IRM_616_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_616_LEN    8
#define GICD_REGS_GICD_AFFINITY2_616_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_616_LEN    8
#define GICD_REGS_GICD_AFFINITY1_616_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_616_LEN    8
#define GICD_REGS_GICD_AFFINITY0_616_OFFSET 0

#define GICD_REGS_GICD_IRM_617_LEN          1
#define GICD_REGS_GICD_IRM_617_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_617_LEN    8
#define GICD_REGS_GICD_AFFINITY2_617_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_617_LEN    8
#define GICD_REGS_GICD_AFFINITY1_617_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_617_LEN    8
#define GICD_REGS_GICD_AFFINITY0_617_OFFSET 0

#define GICD_REGS_GICD_IRM_618_LEN          1
#define GICD_REGS_GICD_IRM_618_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_618_LEN    8
#define GICD_REGS_GICD_AFFINITY2_618_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_618_LEN    8
#define GICD_REGS_GICD_AFFINITY1_618_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_618_LEN    8
#define GICD_REGS_GICD_AFFINITY0_618_OFFSET 0

#define GICD_REGS_GICD_IRM_619_LEN          1
#define GICD_REGS_GICD_IRM_619_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_619_LEN    8
#define GICD_REGS_GICD_AFFINITY2_619_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_619_LEN    8
#define GICD_REGS_GICD_AFFINITY1_619_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_619_LEN    8
#define GICD_REGS_GICD_AFFINITY0_619_OFFSET 0

#define GICD_REGS_GICD_IRM_620_LEN          1
#define GICD_REGS_GICD_IRM_620_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_620_LEN    8
#define GICD_REGS_GICD_AFFINITY2_620_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_620_LEN    8
#define GICD_REGS_GICD_AFFINITY1_620_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_620_LEN    8
#define GICD_REGS_GICD_AFFINITY0_620_OFFSET 0

#define GICD_REGS_GICD_IRM_621_LEN          1
#define GICD_REGS_GICD_IRM_621_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_621_LEN    8
#define GICD_REGS_GICD_AFFINITY2_621_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_621_LEN    8
#define GICD_REGS_GICD_AFFINITY1_621_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_621_LEN    8
#define GICD_REGS_GICD_AFFINITY0_621_OFFSET 0

#define GICD_REGS_GICD_IRM_622_LEN          1
#define GICD_REGS_GICD_IRM_622_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_622_LEN    8
#define GICD_REGS_GICD_AFFINITY2_622_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_622_LEN    8
#define GICD_REGS_GICD_AFFINITY1_622_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_622_LEN    8
#define GICD_REGS_GICD_AFFINITY0_622_OFFSET 0

#define GICD_REGS_GICD_IRM_623_LEN          1
#define GICD_REGS_GICD_IRM_623_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_623_LEN    8
#define GICD_REGS_GICD_AFFINITY2_623_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_623_LEN    8
#define GICD_REGS_GICD_AFFINITY1_623_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_623_LEN    8
#define GICD_REGS_GICD_AFFINITY0_623_OFFSET 0

#define GICD_REGS_GICD_IRM_624_LEN          1
#define GICD_REGS_GICD_IRM_624_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_624_LEN    8
#define GICD_REGS_GICD_AFFINITY2_624_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_624_LEN    8
#define GICD_REGS_GICD_AFFINITY1_624_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_624_LEN    8
#define GICD_REGS_GICD_AFFINITY0_624_OFFSET 0

#define GICD_REGS_GICD_IRM_625_LEN          1
#define GICD_REGS_GICD_IRM_625_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_625_LEN    8
#define GICD_REGS_GICD_AFFINITY2_625_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_625_LEN    8
#define GICD_REGS_GICD_AFFINITY1_625_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_625_LEN    8
#define GICD_REGS_GICD_AFFINITY0_625_OFFSET 0

#define GICD_REGS_GICD_IRM_626_LEN          1
#define GICD_REGS_GICD_IRM_626_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_626_LEN    8
#define GICD_REGS_GICD_AFFINITY2_626_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_626_LEN    8
#define GICD_REGS_GICD_AFFINITY1_626_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_626_LEN    8
#define GICD_REGS_GICD_AFFINITY0_626_OFFSET 0

#define GICD_REGS_GICD_IRM_627_LEN          1
#define GICD_REGS_GICD_IRM_627_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_627_LEN    8
#define GICD_REGS_GICD_AFFINITY2_627_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_627_LEN    8
#define GICD_REGS_GICD_AFFINITY1_627_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_627_LEN    8
#define GICD_REGS_GICD_AFFINITY0_627_OFFSET 0

#define GICD_REGS_GICD_IRM_628_LEN          1
#define GICD_REGS_GICD_IRM_628_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_628_LEN    8
#define GICD_REGS_GICD_AFFINITY2_628_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_628_LEN    8
#define GICD_REGS_GICD_AFFINITY1_628_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_628_LEN    8
#define GICD_REGS_GICD_AFFINITY0_628_OFFSET 0

#define GICD_REGS_GICD_IRM_629_LEN          1
#define GICD_REGS_GICD_IRM_629_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_629_LEN    8
#define GICD_REGS_GICD_AFFINITY2_629_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_629_LEN    8
#define GICD_REGS_GICD_AFFINITY1_629_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_629_LEN    8
#define GICD_REGS_GICD_AFFINITY0_629_OFFSET 0

#define GICD_REGS_GICD_IRM_630_LEN          1
#define GICD_REGS_GICD_IRM_630_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_630_LEN    8
#define GICD_REGS_GICD_AFFINITY2_630_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_630_LEN    8
#define GICD_REGS_GICD_AFFINITY1_630_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_630_LEN    8
#define GICD_REGS_GICD_AFFINITY0_630_OFFSET 0

#define GICD_REGS_GICD_IRM_631_LEN          1
#define GICD_REGS_GICD_IRM_631_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_631_LEN    8
#define GICD_REGS_GICD_AFFINITY2_631_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_631_LEN    8
#define GICD_REGS_GICD_AFFINITY1_631_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_631_LEN    8
#define GICD_REGS_GICD_AFFINITY0_631_OFFSET 0

#define GICD_REGS_GICD_IRM_632_LEN          1
#define GICD_REGS_GICD_IRM_632_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_632_LEN    8
#define GICD_REGS_GICD_AFFINITY2_632_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_632_LEN    8
#define GICD_REGS_GICD_AFFINITY1_632_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_632_LEN    8
#define GICD_REGS_GICD_AFFINITY0_632_OFFSET 0

#define GICD_REGS_GICD_IRM_633_LEN          1
#define GICD_REGS_GICD_IRM_633_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_633_LEN    8
#define GICD_REGS_GICD_AFFINITY2_633_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_633_LEN    8
#define GICD_REGS_GICD_AFFINITY1_633_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_633_LEN    8
#define GICD_REGS_GICD_AFFINITY0_633_OFFSET 0

#define GICD_REGS_GICD_IRM_634_LEN          1
#define GICD_REGS_GICD_IRM_634_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_634_LEN    8
#define GICD_REGS_GICD_AFFINITY2_634_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_634_LEN    8
#define GICD_REGS_GICD_AFFINITY1_634_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_634_LEN    8
#define GICD_REGS_GICD_AFFINITY0_634_OFFSET 0

#define GICD_REGS_GICD_IRM_635_LEN          1
#define GICD_REGS_GICD_IRM_635_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_635_LEN    8
#define GICD_REGS_GICD_AFFINITY2_635_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_635_LEN    8
#define GICD_REGS_GICD_AFFINITY1_635_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_635_LEN    8
#define GICD_REGS_GICD_AFFINITY0_635_OFFSET 0

#define GICD_REGS_GICD_IRM_636_LEN          1
#define GICD_REGS_GICD_IRM_636_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_636_LEN    8
#define GICD_REGS_GICD_AFFINITY2_636_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_636_LEN    8
#define GICD_REGS_GICD_AFFINITY1_636_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_636_LEN    8
#define GICD_REGS_GICD_AFFINITY0_636_OFFSET 0

#define GICD_REGS_GICD_IRM_637_LEN          1
#define GICD_REGS_GICD_IRM_637_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_637_LEN    8
#define GICD_REGS_GICD_AFFINITY2_637_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_637_LEN    8
#define GICD_REGS_GICD_AFFINITY1_637_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_637_LEN    8
#define GICD_REGS_GICD_AFFINITY0_637_OFFSET 0

#define GICD_REGS_GICD_IRM_638_LEN          1
#define GICD_REGS_GICD_IRM_638_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_638_LEN    8
#define GICD_REGS_GICD_AFFINITY2_638_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_638_LEN    8
#define GICD_REGS_GICD_AFFINITY1_638_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_638_LEN    8
#define GICD_REGS_GICD_AFFINITY0_638_OFFSET 0

#define GICD_REGS_GICD_IRM_639_LEN          1
#define GICD_REGS_GICD_IRM_639_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_639_LEN    8
#define GICD_REGS_GICD_AFFINITY2_639_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_639_LEN    8
#define GICD_REGS_GICD_AFFINITY1_639_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_639_LEN    8
#define GICD_REGS_GICD_AFFINITY0_639_OFFSET 0

#define GICD_REGS_GICD_IRM_640_LEN          1
#define GICD_REGS_GICD_IRM_640_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_640_LEN    8
#define GICD_REGS_GICD_AFFINITY2_640_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_640_LEN    8
#define GICD_REGS_GICD_AFFINITY1_640_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_640_LEN    8
#define GICD_REGS_GICD_AFFINITY0_640_OFFSET 0

#define GICD_REGS_GICD_IRM_641_LEN          1
#define GICD_REGS_GICD_IRM_641_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_641_LEN    8
#define GICD_REGS_GICD_AFFINITY2_641_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_641_LEN    8
#define GICD_REGS_GICD_AFFINITY1_641_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_641_LEN    8
#define GICD_REGS_GICD_AFFINITY0_641_OFFSET 0

#define GICD_REGS_GICD_IRM_642_LEN          1
#define GICD_REGS_GICD_IRM_642_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_642_LEN    8
#define GICD_REGS_GICD_AFFINITY2_642_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_642_LEN    8
#define GICD_REGS_GICD_AFFINITY1_642_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_642_LEN    8
#define GICD_REGS_GICD_AFFINITY0_642_OFFSET 0

#define GICD_REGS_GICD_IRM_643_LEN          1
#define GICD_REGS_GICD_IRM_643_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_643_LEN    8
#define GICD_REGS_GICD_AFFINITY2_643_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_643_LEN    8
#define GICD_REGS_GICD_AFFINITY1_643_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_643_LEN    8
#define GICD_REGS_GICD_AFFINITY0_643_OFFSET 0

#define GICD_REGS_GICD_IRM_644_LEN          1
#define GICD_REGS_GICD_IRM_644_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_644_LEN    8
#define GICD_REGS_GICD_AFFINITY2_644_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_644_LEN    8
#define GICD_REGS_GICD_AFFINITY1_644_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_644_LEN    8
#define GICD_REGS_GICD_AFFINITY0_644_OFFSET 0

#define GICD_REGS_GICD_IRM_645_LEN          1
#define GICD_REGS_GICD_IRM_645_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_645_LEN    8
#define GICD_REGS_GICD_AFFINITY2_645_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_645_LEN    8
#define GICD_REGS_GICD_AFFINITY1_645_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_645_LEN    8
#define GICD_REGS_GICD_AFFINITY0_645_OFFSET 0

#define GICD_REGS_GICD_IRM_646_LEN          1
#define GICD_REGS_GICD_IRM_646_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_646_LEN    8
#define GICD_REGS_GICD_AFFINITY2_646_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_646_LEN    8
#define GICD_REGS_GICD_AFFINITY1_646_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_646_LEN    8
#define GICD_REGS_GICD_AFFINITY0_646_OFFSET 0

#define GICD_REGS_GICD_IRM_647_LEN          1
#define GICD_REGS_GICD_IRM_647_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_647_LEN    8
#define GICD_REGS_GICD_AFFINITY2_647_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_647_LEN    8
#define GICD_REGS_GICD_AFFINITY1_647_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_647_LEN    8
#define GICD_REGS_GICD_AFFINITY0_647_OFFSET 0

#define GICD_REGS_GICD_IRM_648_LEN          1
#define GICD_REGS_GICD_IRM_648_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_648_LEN    8
#define GICD_REGS_GICD_AFFINITY2_648_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_648_LEN    8
#define GICD_REGS_GICD_AFFINITY1_648_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_648_LEN    8
#define GICD_REGS_GICD_AFFINITY0_648_OFFSET 0

#define GICD_REGS_GICD_IRM_649_LEN          1
#define GICD_REGS_GICD_IRM_649_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_649_LEN    8
#define GICD_REGS_GICD_AFFINITY2_649_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_649_LEN    8
#define GICD_REGS_GICD_AFFINITY1_649_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_649_LEN    8
#define GICD_REGS_GICD_AFFINITY0_649_OFFSET 0

#define GICD_REGS_GICD_IRM_650_LEN          1
#define GICD_REGS_GICD_IRM_650_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_650_LEN    8
#define GICD_REGS_GICD_AFFINITY2_650_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_650_LEN    8
#define GICD_REGS_GICD_AFFINITY1_650_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_650_LEN    8
#define GICD_REGS_GICD_AFFINITY0_650_OFFSET 0

#define GICD_REGS_GICD_IRM_651_LEN          1
#define GICD_REGS_GICD_IRM_651_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_651_LEN    8
#define GICD_REGS_GICD_AFFINITY2_651_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_651_LEN    8
#define GICD_REGS_GICD_AFFINITY1_651_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_651_LEN    8
#define GICD_REGS_GICD_AFFINITY0_651_OFFSET 0

#define GICD_REGS_GICD_IRM_652_LEN          1
#define GICD_REGS_GICD_IRM_652_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_652_LEN    8
#define GICD_REGS_GICD_AFFINITY2_652_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_652_LEN    8
#define GICD_REGS_GICD_AFFINITY1_652_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_652_LEN    8
#define GICD_REGS_GICD_AFFINITY0_652_OFFSET 0

#define GICD_REGS_GICD_IRM_653_LEN          1
#define GICD_REGS_GICD_IRM_653_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_653_LEN    8
#define GICD_REGS_GICD_AFFINITY2_653_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_653_LEN    8
#define GICD_REGS_GICD_AFFINITY1_653_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_653_LEN    8
#define GICD_REGS_GICD_AFFINITY0_653_OFFSET 0

#define GICD_REGS_GICD_IRM_654_LEN          1
#define GICD_REGS_GICD_IRM_654_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_654_LEN    8
#define GICD_REGS_GICD_AFFINITY2_654_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_654_LEN    8
#define GICD_REGS_GICD_AFFINITY1_654_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_654_LEN    8
#define GICD_REGS_GICD_AFFINITY0_654_OFFSET 0

#define GICD_REGS_GICD_IRM_655_LEN          1
#define GICD_REGS_GICD_IRM_655_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_655_LEN    8
#define GICD_REGS_GICD_AFFINITY2_655_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_655_LEN    8
#define GICD_REGS_GICD_AFFINITY1_655_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_655_LEN    8
#define GICD_REGS_GICD_AFFINITY0_655_OFFSET 0

#define GICD_REGS_GICD_IRM_656_LEN          1
#define GICD_REGS_GICD_IRM_656_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_656_LEN    8
#define GICD_REGS_GICD_AFFINITY2_656_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_656_LEN    8
#define GICD_REGS_GICD_AFFINITY1_656_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_656_LEN    8
#define GICD_REGS_GICD_AFFINITY0_656_OFFSET 0

#define GICD_REGS_GICD_IRM_657_LEN          1
#define GICD_REGS_GICD_IRM_657_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_657_LEN    8
#define GICD_REGS_GICD_AFFINITY2_657_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_657_LEN    8
#define GICD_REGS_GICD_AFFINITY1_657_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_657_LEN    8
#define GICD_REGS_GICD_AFFINITY0_657_OFFSET 0

#define GICD_REGS_GICD_IRM_658_LEN          1
#define GICD_REGS_GICD_IRM_658_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_658_LEN    8
#define GICD_REGS_GICD_AFFINITY2_658_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_658_LEN    8
#define GICD_REGS_GICD_AFFINITY1_658_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_658_LEN    8
#define GICD_REGS_GICD_AFFINITY0_658_OFFSET 0

#define GICD_REGS_GICD_IRM_659_LEN          1
#define GICD_REGS_GICD_IRM_659_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_659_LEN    8
#define GICD_REGS_GICD_AFFINITY2_659_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_659_LEN    8
#define GICD_REGS_GICD_AFFINITY1_659_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_659_LEN    8
#define GICD_REGS_GICD_AFFINITY0_659_OFFSET 0

#define GICD_REGS_GICD_IRM_660_LEN          1
#define GICD_REGS_GICD_IRM_660_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_660_LEN    8
#define GICD_REGS_GICD_AFFINITY2_660_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_660_LEN    8
#define GICD_REGS_GICD_AFFINITY1_660_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_660_LEN    8
#define GICD_REGS_GICD_AFFINITY0_660_OFFSET 0

#define GICD_REGS_GICD_IRM_661_LEN          1
#define GICD_REGS_GICD_IRM_661_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_661_LEN    8
#define GICD_REGS_GICD_AFFINITY2_661_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_661_LEN    8
#define GICD_REGS_GICD_AFFINITY1_661_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_661_LEN    8
#define GICD_REGS_GICD_AFFINITY0_661_OFFSET 0

#define GICD_REGS_GICD_IRM_662_LEN          1
#define GICD_REGS_GICD_IRM_662_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_662_LEN    8
#define GICD_REGS_GICD_AFFINITY2_662_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_662_LEN    8
#define GICD_REGS_GICD_AFFINITY1_662_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_662_LEN    8
#define GICD_REGS_GICD_AFFINITY0_662_OFFSET 0

#define GICD_REGS_GICD_IRM_663_LEN          1
#define GICD_REGS_GICD_IRM_663_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_663_LEN    8
#define GICD_REGS_GICD_AFFINITY2_663_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_663_LEN    8
#define GICD_REGS_GICD_AFFINITY1_663_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_663_LEN    8
#define GICD_REGS_GICD_AFFINITY0_663_OFFSET 0

#define GICD_REGS_GICD_IRM_664_LEN          1
#define GICD_REGS_GICD_IRM_664_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_664_LEN    8
#define GICD_REGS_GICD_AFFINITY2_664_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_664_LEN    8
#define GICD_REGS_GICD_AFFINITY1_664_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_664_LEN    8
#define GICD_REGS_GICD_AFFINITY0_664_OFFSET 0

#define GICD_REGS_GICD_IRM_665_LEN          1
#define GICD_REGS_GICD_IRM_665_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_665_LEN    8
#define GICD_REGS_GICD_AFFINITY2_665_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_665_LEN    8
#define GICD_REGS_GICD_AFFINITY1_665_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_665_LEN    8
#define GICD_REGS_GICD_AFFINITY0_665_OFFSET 0

#define GICD_REGS_GICD_IRM_666_LEN          1
#define GICD_REGS_GICD_IRM_666_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_666_LEN    8
#define GICD_REGS_GICD_AFFINITY2_666_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_666_LEN    8
#define GICD_REGS_GICD_AFFINITY1_666_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_666_LEN    8
#define GICD_REGS_GICD_AFFINITY0_666_OFFSET 0

#define GICD_REGS_GICD_IRM_667_LEN          1
#define GICD_REGS_GICD_IRM_667_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_667_LEN    8
#define GICD_REGS_GICD_AFFINITY2_667_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_667_LEN    8
#define GICD_REGS_GICD_AFFINITY1_667_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_667_LEN    8
#define GICD_REGS_GICD_AFFINITY0_667_OFFSET 0

#define GICD_REGS_GICD_IRM_668_LEN          1
#define GICD_REGS_GICD_IRM_668_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_668_LEN    8
#define GICD_REGS_GICD_AFFINITY2_668_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_668_LEN    8
#define GICD_REGS_GICD_AFFINITY1_668_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_668_LEN    8
#define GICD_REGS_GICD_AFFINITY0_668_OFFSET 0

#define GICD_REGS_GICD_IRM_669_LEN          1
#define GICD_REGS_GICD_IRM_669_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_669_LEN    8
#define GICD_REGS_GICD_AFFINITY2_669_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_669_LEN    8
#define GICD_REGS_GICD_AFFINITY1_669_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_669_LEN    8
#define GICD_REGS_GICD_AFFINITY0_669_OFFSET 0

#define GICD_REGS_GICD_IRM_670_LEN          1
#define GICD_REGS_GICD_IRM_670_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_670_LEN    8
#define GICD_REGS_GICD_AFFINITY2_670_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_670_LEN    8
#define GICD_REGS_GICD_AFFINITY1_670_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_670_LEN    8
#define GICD_REGS_GICD_AFFINITY0_670_OFFSET 0

#define GICD_REGS_GICD_IRM_671_LEN          1
#define GICD_REGS_GICD_IRM_671_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_671_LEN    8
#define GICD_REGS_GICD_AFFINITY2_671_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_671_LEN    8
#define GICD_REGS_GICD_AFFINITY1_671_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_671_LEN    8
#define GICD_REGS_GICD_AFFINITY0_671_OFFSET 0

#define GICD_REGS_GICD_IRM_672_LEN          1
#define GICD_REGS_GICD_IRM_672_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_672_LEN    8
#define GICD_REGS_GICD_AFFINITY2_672_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_672_LEN    8
#define GICD_REGS_GICD_AFFINITY1_672_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_672_LEN    8
#define GICD_REGS_GICD_AFFINITY0_672_OFFSET 0

#define GICD_REGS_GICD_IRM_673_LEN          1
#define GICD_REGS_GICD_IRM_673_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_673_LEN    8
#define GICD_REGS_GICD_AFFINITY2_673_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_673_LEN    8
#define GICD_REGS_GICD_AFFINITY1_673_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_673_LEN    8
#define GICD_REGS_GICD_AFFINITY0_673_OFFSET 0

#define GICD_REGS_GICD_IRM_674_LEN          1
#define GICD_REGS_GICD_IRM_674_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_674_LEN    8
#define GICD_REGS_GICD_AFFINITY2_674_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_674_LEN    8
#define GICD_REGS_GICD_AFFINITY1_674_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_674_LEN    8
#define GICD_REGS_GICD_AFFINITY0_674_OFFSET 0

#define GICD_REGS_GICD_IRM_675_LEN          1
#define GICD_REGS_GICD_IRM_675_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_675_LEN    8
#define GICD_REGS_GICD_AFFINITY2_675_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_675_LEN    8
#define GICD_REGS_GICD_AFFINITY1_675_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_675_LEN    8
#define GICD_REGS_GICD_AFFINITY0_675_OFFSET 0

#define GICD_REGS_GICD_IRM_676_LEN          1
#define GICD_REGS_GICD_IRM_676_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_676_LEN    8
#define GICD_REGS_GICD_AFFINITY2_676_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_676_LEN    8
#define GICD_REGS_GICD_AFFINITY1_676_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_676_LEN    8
#define GICD_REGS_GICD_AFFINITY0_676_OFFSET 0

#define GICD_REGS_GICD_IRM_677_LEN          1
#define GICD_REGS_GICD_IRM_677_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_677_LEN    8
#define GICD_REGS_GICD_AFFINITY2_677_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_677_LEN    8
#define GICD_REGS_GICD_AFFINITY1_677_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_677_LEN    8
#define GICD_REGS_GICD_AFFINITY0_677_OFFSET 0

#define GICD_REGS_GICD_IRM_678_LEN          1
#define GICD_REGS_GICD_IRM_678_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_678_LEN    8
#define GICD_REGS_GICD_AFFINITY2_678_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_678_LEN    8
#define GICD_REGS_GICD_AFFINITY1_678_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_678_LEN    8
#define GICD_REGS_GICD_AFFINITY0_678_OFFSET 0

#define GICD_REGS_GICD_IRM_679_LEN          1
#define GICD_REGS_GICD_IRM_679_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_679_LEN    8
#define GICD_REGS_GICD_AFFINITY2_679_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_679_LEN    8
#define GICD_REGS_GICD_AFFINITY1_679_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_679_LEN    8
#define GICD_REGS_GICD_AFFINITY0_679_OFFSET 0

#define GICD_REGS_GICD_IRM_680_LEN          1
#define GICD_REGS_GICD_IRM_680_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_680_LEN    8
#define GICD_REGS_GICD_AFFINITY2_680_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_680_LEN    8
#define GICD_REGS_GICD_AFFINITY1_680_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_680_LEN    8
#define GICD_REGS_GICD_AFFINITY0_680_OFFSET 0

#define GICD_REGS_GICD_IRM_681_LEN          1
#define GICD_REGS_GICD_IRM_681_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_681_LEN    8
#define GICD_REGS_GICD_AFFINITY2_681_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_681_LEN    8
#define GICD_REGS_GICD_AFFINITY1_681_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_681_LEN    8
#define GICD_REGS_GICD_AFFINITY0_681_OFFSET 0

#define GICD_REGS_GICD_IRM_682_LEN          1
#define GICD_REGS_GICD_IRM_682_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_682_LEN    8
#define GICD_REGS_GICD_AFFINITY2_682_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_682_LEN    8
#define GICD_REGS_GICD_AFFINITY1_682_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_682_LEN    8
#define GICD_REGS_GICD_AFFINITY0_682_OFFSET 0

#define GICD_REGS_GICD_IRM_683_LEN          1
#define GICD_REGS_GICD_IRM_683_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_683_LEN    8
#define GICD_REGS_GICD_AFFINITY2_683_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_683_LEN    8
#define GICD_REGS_GICD_AFFINITY1_683_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_683_LEN    8
#define GICD_REGS_GICD_AFFINITY0_683_OFFSET 0

#define GICD_REGS_GICD_IRM_684_LEN          1
#define GICD_REGS_GICD_IRM_684_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_684_LEN    8
#define GICD_REGS_GICD_AFFINITY2_684_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_684_LEN    8
#define GICD_REGS_GICD_AFFINITY1_684_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_684_LEN    8
#define GICD_REGS_GICD_AFFINITY0_684_OFFSET 0

#define GICD_REGS_GICD_IRM_685_LEN          1
#define GICD_REGS_GICD_IRM_685_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_685_LEN    8
#define GICD_REGS_GICD_AFFINITY2_685_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_685_LEN    8
#define GICD_REGS_GICD_AFFINITY1_685_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_685_LEN    8
#define GICD_REGS_GICD_AFFINITY0_685_OFFSET 0

#define GICD_REGS_GICD_IRM_686_LEN          1
#define GICD_REGS_GICD_IRM_686_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_686_LEN    8
#define GICD_REGS_GICD_AFFINITY2_686_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_686_LEN    8
#define GICD_REGS_GICD_AFFINITY1_686_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_686_LEN    8
#define GICD_REGS_GICD_AFFINITY0_686_OFFSET 0

#define GICD_REGS_GICD_IRM_687_LEN          1
#define GICD_REGS_GICD_IRM_687_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_687_LEN    8
#define GICD_REGS_GICD_AFFINITY2_687_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_687_LEN    8
#define GICD_REGS_GICD_AFFINITY1_687_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_687_LEN    8
#define GICD_REGS_GICD_AFFINITY0_687_OFFSET 0

#define GICD_REGS_GICD_IRM_688_LEN          1
#define GICD_REGS_GICD_IRM_688_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_688_LEN    8
#define GICD_REGS_GICD_AFFINITY2_688_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_688_LEN    8
#define GICD_REGS_GICD_AFFINITY1_688_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_688_LEN    8
#define GICD_REGS_GICD_AFFINITY0_688_OFFSET 0

#define GICD_REGS_GICD_IRM_689_LEN          1
#define GICD_REGS_GICD_IRM_689_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_689_LEN    8
#define GICD_REGS_GICD_AFFINITY2_689_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_689_LEN    8
#define GICD_REGS_GICD_AFFINITY1_689_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_689_LEN    8
#define GICD_REGS_GICD_AFFINITY0_689_OFFSET 0

#define GICD_REGS_GICD_IRM_690_LEN          1
#define GICD_REGS_GICD_IRM_690_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_690_LEN    8
#define GICD_REGS_GICD_AFFINITY2_690_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_690_LEN    8
#define GICD_REGS_GICD_AFFINITY1_690_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_690_LEN    8
#define GICD_REGS_GICD_AFFINITY0_690_OFFSET 0

#define GICD_REGS_GICD_IRM_691_LEN          1
#define GICD_REGS_GICD_IRM_691_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_691_LEN    8
#define GICD_REGS_GICD_AFFINITY2_691_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_691_LEN    8
#define GICD_REGS_GICD_AFFINITY1_691_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_691_LEN    8
#define GICD_REGS_GICD_AFFINITY0_691_OFFSET 0

#define GICD_REGS_GICD_IRM_692_LEN          1
#define GICD_REGS_GICD_IRM_692_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_692_LEN    8
#define GICD_REGS_GICD_AFFINITY2_692_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_692_LEN    8
#define GICD_REGS_GICD_AFFINITY1_692_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_692_LEN    8
#define GICD_REGS_GICD_AFFINITY0_692_OFFSET 0

#define GICD_REGS_GICD_IRM_693_LEN          1
#define GICD_REGS_GICD_IRM_693_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_693_LEN    8
#define GICD_REGS_GICD_AFFINITY2_693_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_693_LEN    8
#define GICD_REGS_GICD_AFFINITY1_693_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_693_LEN    8
#define GICD_REGS_GICD_AFFINITY0_693_OFFSET 0

#define GICD_REGS_GICD_IRM_694_LEN          1
#define GICD_REGS_GICD_IRM_694_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_694_LEN    8
#define GICD_REGS_GICD_AFFINITY2_694_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_694_LEN    8
#define GICD_REGS_GICD_AFFINITY1_694_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_694_LEN    8
#define GICD_REGS_GICD_AFFINITY0_694_OFFSET 0

#define GICD_REGS_GICD_IRM_695_LEN          1
#define GICD_REGS_GICD_IRM_695_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_695_LEN    8
#define GICD_REGS_GICD_AFFINITY2_695_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_695_LEN    8
#define GICD_REGS_GICD_AFFINITY1_695_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_695_LEN    8
#define GICD_REGS_GICD_AFFINITY0_695_OFFSET 0

#define GICD_REGS_GICD_IRM_696_LEN          1
#define GICD_REGS_GICD_IRM_696_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_696_LEN    8
#define GICD_REGS_GICD_AFFINITY2_696_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_696_LEN    8
#define GICD_REGS_GICD_AFFINITY1_696_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_696_LEN    8
#define GICD_REGS_GICD_AFFINITY0_696_OFFSET 0

#define GICD_REGS_GICD_IRM_697_LEN          1
#define GICD_REGS_GICD_IRM_697_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_697_LEN    8
#define GICD_REGS_GICD_AFFINITY2_697_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_697_LEN    8
#define GICD_REGS_GICD_AFFINITY1_697_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_697_LEN    8
#define GICD_REGS_GICD_AFFINITY0_697_OFFSET 0

#define GICD_REGS_GICD_IRM_698_LEN          1
#define GICD_REGS_GICD_IRM_698_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_698_LEN    8
#define GICD_REGS_GICD_AFFINITY2_698_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_698_LEN    8
#define GICD_REGS_GICD_AFFINITY1_698_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_698_LEN    8
#define GICD_REGS_GICD_AFFINITY0_698_OFFSET 0

#define GICD_REGS_GICD_IRM_699_LEN          1
#define GICD_REGS_GICD_IRM_699_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_699_LEN    8
#define GICD_REGS_GICD_AFFINITY2_699_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_699_LEN    8
#define GICD_REGS_GICD_AFFINITY1_699_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_699_LEN    8
#define GICD_REGS_GICD_AFFINITY0_699_OFFSET 0

#define GICD_REGS_GICD_IRM_700_LEN          1
#define GICD_REGS_GICD_IRM_700_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_700_LEN    8
#define GICD_REGS_GICD_AFFINITY2_700_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_700_LEN    8
#define GICD_REGS_GICD_AFFINITY1_700_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_700_LEN    8
#define GICD_REGS_GICD_AFFINITY0_700_OFFSET 0

#define GICD_REGS_GICD_IRM_701_LEN          1
#define GICD_REGS_GICD_IRM_701_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_701_LEN    8
#define GICD_REGS_GICD_AFFINITY2_701_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_701_LEN    8
#define GICD_REGS_GICD_AFFINITY1_701_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_701_LEN    8
#define GICD_REGS_GICD_AFFINITY0_701_OFFSET 0

#define GICD_REGS_GICD_IRM_702_LEN          1
#define GICD_REGS_GICD_IRM_702_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_702_LEN    8
#define GICD_REGS_GICD_AFFINITY2_702_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_702_LEN    8
#define GICD_REGS_GICD_AFFINITY1_702_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_702_LEN    8
#define GICD_REGS_GICD_AFFINITY0_702_OFFSET 0

#define GICD_REGS_GICD_IRM_703_LEN          1
#define GICD_REGS_GICD_IRM_703_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_703_LEN    8
#define GICD_REGS_GICD_AFFINITY2_703_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_703_LEN    8
#define GICD_REGS_GICD_AFFINITY1_703_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_703_LEN    8
#define GICD_REGS_GICD_AFFINITY0_703_OFFSET 0

#define GICD_REGS_GICD_IRM_704_LEN          1
#define GICD_REGS_GICD_IRM_704_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_704_LEN    8
#define GICD_REGS_GICD_AFFINITY2_704_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_704_LEN    8
#define GICD_REGS_GICD_AFFINITY1_704_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_704_LEN    8
#define GICD_REGS_GICD_AFFINITY0_704_OFFSET 0

#define GICD_REGS_GICD_IRM_705_LEN          1
#define GICD_REGS_GICD_IRM_705_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_705_LEN    8
#define GICD_REGS_GICD_AFFINITY2_705_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_705_LEN    8
#define GICD_REGS_GICD_AFFINITY1_705_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_705_LEN    8
#define GICD_REGS_GICD_AFFINITY0_705_OFFSET 0

#define GICD_REGS_GICD_IRM_706_LEN          1
#define GICD_REGS_GICD_IRM_706_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_706_LEN    8
#define GICD_REGS_GICD_AFFINITY2_706_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_706_LEN    8
#define GICD_REGS_GICD_AFFINITY1_706_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_706_LEN    8
#define GICD_REGS_GICD_AFFINITY0_706_OFFSET 0

#define GICD_REGS_GICD_IRM_707_LEN          1
#define GICD_REGS_GICD_IRM_707_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_707_LEN    8
#define GICD_REGS_GICD_AFFINITY2_707_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_707_LEN    8
#define GICD_REGS_GICD_AFFINITY1_707_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_707_LEN    8
#define GICD_REGS_GICD_AFFINITY0_707_OFFSET 0

#define GICD_REGS_GICD_IRM_708_LEN          1
#define GICD_REGS_GICD_IRM_708_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_708_LEN    8
#define GICD_REGS_GICD_AFFINITY2_708_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_708_LEN    8
#define GICD_REGS_GICD_AFFINITY1_708_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_708_LEN    8
#define GICD_REGS_GICD_AFFINITY0_708_OFFSET 0

#define GICD_REGS_GICD_IRM_709_LEN          1
#define GICD_REGS_GICD_IRM_709_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_709_LEN    8
#define GICD_REGS_GICD_AFFINITY2_709_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_709_LEN    8
#define GICD_REGS_GICD_AFFINITY1_709_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_709_LEN    8
#define GICD_REGS_GICD_AFFINITY0_709_OFFSET 0

#define GICD_REGS_GICD_IRM_710_LEN          1
#define GICD_REGS_GICD_IRM_710_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_710_LEN    8
#define GICD_REGS_GICD_AFFINITY2_710_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_710_LEN    8
#define GICD_REGS_GICD_AFFINITY1_710_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_710_LEN    8
#define GICD_REGS_GICD_AFFINITY0_710_OFFSET 0

#define GICD_REGS_GICD_IRM_711_LEN          1
#define GICD_REGS_GICD_IRM_711_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_711_LEN    8
#define GICD_REGS_GICD_AFFINITY2_711_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_711_LEN    8
#define GICD_REGS_GICD_AFFINITY1_711_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_711_LEN    8
#define GICD_REGS_GICD_AFFINITY0_711_OFFSET 0

#define GICD_REGS_GICD_IRM_712_LEN          1
#define GICD_REGS_GICD_IRM_712_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_712_LEN    8
#define GICD_REGS_GICD_AFFINITY2_712_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_712_LEN    8
#define GICD_REGS_GICD_AFFINITY1_712_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_712_LEN    8
#define GICD_REGS_GICD_AFFINITY0_712_OFFSET 0

#define GICD_REGS_GICD_IRM_713_LEN          1
#define GICD_REGS_GICD_IRM_713_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_713_LEN    8
#define GICD_REGS_GICD_AFFINITY2_713_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_713_LEN    8
#define GICD_REGS_GICD_AFFINITY1_713_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_713_LEN    8
#define GICD_REGS_GICD_AFFINITY0_713_OFFSET 0

#define GICD_REGS_GICD_IRM_714_LEN          1
#define GICD_REGS_GICD_IRM_714_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_714_LEN    8
#define GICD_REGS_GICD_AFFINITY2_714_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_714_LEN    8
#define GICD_REGS_GICD_AFFINITY1_714_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_714_LEN    8
#define GICD_REGS_GICD_AFFINITY0_714_OFFSET 0

#define GICD_REGS_GICD_IRM_715_LEN          1
#define GICD_REGS_GICD_IRM_715_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_715_LEN    8
#define GICD_REGS_GICD_AFFINITY2_715_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_715_LEN    8
#define GICD_REGS_GICD_AFFINITY1_715_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_715_LEN    8
#define GICD_REGS_GICD_AFFINITY0_715_OFFSET 0

#define GICD_REGS_GICD_IRM_716_LEN          1
#define GICD_REGS_GICD_IRM_716_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_716_LEN    8
#define GICD_REGS_GICD_AFFINITY2_716_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_716_LEN    8
#define GICD_REGS_GICD_AFFINITY1_716_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_716_LEN    8
#define GICD_REGS_GICD_AFFINITY0_716_OFFSET 0

#define GICD_REGS_GICD_IRM_717_LEN          1
#define GICD_REGS_GICD_IRM_717_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_717_LEN    8
#define GICD_REGS_GICD_AFFINITY2_717_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_717_LEN    8
#define GICD_REGS_GICD_AFFINITY1_717_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_717_LEN    8
#define GICD_REGS_GICD_AFFINITY0_717_OFFSET 0

#define GICD_REGS_GICD_IRM_718_LEN          1
#define GICD_REGS_GICD_IRM_718_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_718_LEN    8
#define GICD_REGS_GICD_AFFINITY2_718_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_718_LEN    8
#define GICD_REGS_GICD_AFFINITY1_718_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_718_LEN    8
#define GICD_REGS_GICD_AFFINITY0_718_OFFSET 0

#define GICD_REGS_GICD_IRM_719_LEN          1
#define GICD_REGS_GICD_IRM_719_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_719_LEN    8
#define GICD_REGS_GICD_AFFINITY2_719_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_719_LEN    8
#define GICD_REGS_GICD_AFFINITY1_719_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_719_LEN    8
#define GICD_REGS_GICD_AFFINITY0_719_OFFSET 0

#define GICD_REGS_GICD_IRM_720_LEN          1
#define GICD_REGS_GICD_IRM_720_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_720_LEN    8
#define GICD_REGS_GICD_AFFINITY2_720_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_720_LEN    8
#define GICD_REGS_GICD_AFFINITY1_720_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_720_LEN    8
#define GICD_REGS_GICD_AFFINITY0_720_OFFSET 0

#define GICD_REGS_GICD_IRM_721_LEN          1
#define GICD_REGS_GICD_IRM_721_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_721_LEN    8
#define GICD_REGS_GICD_AFFINITY2_721_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_721_LEN    8
#define GICD_REGS_GICD_AFFINITY1_721_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_721_LEN    8
#define GICD_REGS_GICD_AFFINITY0_721_OFFSET 0

#define GICD_REGS_GICD_IRM_722_LEN          1
#define GICD_REGS_GICD_IRM_722_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_722_LEN    8
#define GICD_REGS_GICD_AFFINITY2_722_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_722_LEN    8
#define GICD_REGS_GICD_AFFINITY1_722_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_722_LEN    8
#define GICD_REGS_GICD_AFFINITY0_722_OFFSET 0

#define GICD_REGS_GICD_IRM_723_LEN          1
#define GICD_REGS_GICD_IRM_723_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_723_LEN    8
#define GICD_REGS_GICD_AFFINITY2_723_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_723_LEN    8
#define GICD_REGS_GICD_AFFINITY1_723_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_723_LEN    8
#define GICD_REGS_GICD_AFFINITY0_723_OFFSET 0

#define GICD_REGS_GICD_IRM_724_LEN          1
#define GICD_REGS_GICD_IRM_724_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_724_LEN    8
#define GICD_REGS_GICD_AFFINITY2_724_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_724_LEN    8
#define GICD_REGS_GICD_AFFINITY1_724_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_724_LEN    8
#define GICD_REGS_GICD_AFFINITY0_724_OFFSET 0

#define GICD_REGS_GICD_IRM_725_LEN          1
#define GICD_REGS_GICD_IRM_725_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_725_LEN    8
#define GICD_REGS_GICD_AFFINITY2_725_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_725_LEN    8
#define GICD_REGS_GICD_AFFINITY1_725_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_725_LEN    8
#define GICD_REGS_GICD_AFFINITY0_725_OFFSET 0

#define GICD_REGS_GICD_IRM_726_LEN          1
#define GICD_REGS_GICD_IRM_726_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_726_LEN    8
#define GICD_REGS_GICD_AFFINITY2_726_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_726_LEN    8
#define GICD_REGS_GICD_AFFINITY1_726_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_726_LEN    8
#define GICD_REGS_GICD_AFFINITY0_726_OFFSET 0

#define GICD_REGS_GICD_IRM_727_LEN          1
#define GICD_REGS_GICD_IRM_727_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_727_LEN    8
#define GICD_REGS_GICD_AFFINITY2_727_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_727_LEN    8
#define GICD_REGS_GICD_AFFINITY1_727_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_727_LEN    8
#define GICD_REGS_GICD_AFFINITY0_727_OFFSET 0

#define GICD_REGS_GICD_IRM_728_LEN          1
#define GICD_REGS_GICD_IRM_728_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_728_LEN    8
#define GICD_REGS_GICD_AFFINITY2_728_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_728_LEN    8
#define GICD_REGS_GICD_AFFINITY1_728_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_728_LEN    8
#define GICD_REGS_GICD_AFFINITY0_728_OFFSET 0

#define GICD_REGS_GICD_IRM_729_LEN          1
#define GICD_REGS_GICD_IRM_729_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_729_LEN    8
#define GICD_REGS_GICD_AFFINITY2_729_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_729_LEN    8
#define GICD_REGS_GICD_AFFINITY1_729_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_729_LEN    8
#define GICD_REGS_GICD_AFFINITY0_729_OFFSET 0

#define GICD_REGS_GICD_IRM_730_LEN          1
#define GICD_REGS_GICD_IRM_730_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_730_LEN    8
#define GICD_REGS_GICD_AFFINITY2_730_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_730_LEN    8
#define GICD_REGS_GICD_AFFINITY1_730_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_730_LEN    8
#define GICD_REGS_GICD_AFFINITY0_730_OFFSET 0

#define GICD_REGS_GICD_IRM_731_LEN          1
#define GICD_REGS_GICD_IRM_731_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_731_LEN    8
#define GICD_REGS_GICD_AFFINITY2_731_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_731_LEN    8
#define GICD_REGS_GICD_AFFINITY1_731_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_731_LEN    8
#define GICD_REGS_GICD_AFFINITY0_731_OFFSET 0

#define GICD_REGS_GICD_IRM_732_LEN          1
#define GICD_REGS_GICD_IRM_732_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_732_LEN    8
#define GICD_REGS_GICD_AFFINITY2_732_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_732_LEN    8
#define GICD_REGS_GICD_AFFINITY1_732_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_732_LEN    8
#define GICD_REGS_GICD_AFFINITY0_732_OFFSET 0

#define GICD_REGS_GICD_IRM_733_LEN          1
#define GICD_REGS_GICD_IRM_733_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_733_LEN    8
#define GICD_REGS_GICD_AFFINITY2_733_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_733_LEN    8
#define GICD_REGS_GICD_AFFINITY1_733_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_733_LEN    8
#define GICD_REGS_GICD_AFFINITY0_733_OFFSET 0

#define GICD_REGS_GICD_IRM_734_LEN          1
#define GICD_REGS_GICD_IRM_734_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_734_LEN    8
#define GICD_REGS_GICD_AFFINITY2_734_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_734_LEN    8
#define GICD_REGS_GICD_AFFINITY1_734_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_734_LEN    8
#define GICD_REGS_GICD_AFFINITY0_734_OFFSET 0

#define GICD_REGS_GICD_IRM_735_LEN          1
#define GICD_REGS_GICD_IRM_735_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_735_LEN    8
#define GICD_REGS_GICD_AFFINITY2_735_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_735_LEN    8
#define GICD_REGS_GICD_AFFINITY1_735_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_735_LEN    8
#define GICD_REGS_GICD_AFFINITY0_735_OFFSET 0

#define GICD_REGS_GICD_IRM_736_LEN          1
#define GICD_REGS_GICD_IRM_736_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_736_LEN    8
#define GICD_REGS_GICD_AFFINITY2_736_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_736_LEN    8
#define GICD_REGS_GICD_AFFINITY1_736_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_736_LEN    8
#define GICD_REGS_GICD_AFFINITY0_736_OFFSET 0

#define GICD_REGS_GICD_IRM_737_LEN          1
#define GICD_REGS_GICD_IRM_737_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_737_LEN    8
#define GICD_REGS_GICD_AFFINITY2_737_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_737_LEN    8
#define GICD_REGS_GICD_AFFINITY1_737_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_737_LEN    8
#define GICD_REGS_GICD_AFFINITY0_737_OFFSET 0

#define GICD_REGS_GICD_IRM_738_LEN          1
#define GICD_REGS_GICD_IRM_738_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_738_LEN    8
#define GICD_REGS_GICD_AFFINITY2_738_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_738_LEN    8
#define GICD_REGS_GICD_AFFINITY1_738_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_738_LEN    8
#define GICD_REGS_GICD_AFFINITY0_738_OFFSET 0

#define GICD_REGS_GICD_IRM_739_LEN          1
#define GICD_REGS_GICD_IRM_739_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_739_LEN    8
#define GICD_REGS_GICD_AFFINITY2_739_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_739_LEN    8
#define GICD_REGS_GICD_AFFINITY1_739_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_739_LEN    8
#define GICD_REGS_GICD_AFFINITY0_739_OFFSET 0

#define GICD_REGS_GICD_IRM_740_LEN          1
#define GICD_REGS_GICD_IRM_740_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_740_LEN    8
#define GICD_REGS_GICD_AFFINITY2_740_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_740_LEN    8
#define GICD_REGS_GICD_AFFINITY1_740_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_740_LEN    8
#define GICD_REGS_GICD_AFFINITY0_740_OFFSET 0

#define GICD_REGS_GICD_IRM_741_LEN          1
#define GICD_REGS_GICD_IRM_741_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_741_LEN    8
#define GICD_REGS_GICD_AFFINITY2_741_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_741_LEN    8
#define GICD_REGS_GICD_AFFINITY1_741_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_741_LEN    8
#define GICD_REGS_GICD_AFFINITY0_741_OFFSET 0

#define GICD_REGS_GICD_IRM_742_LEN          1
#define GICD_REGS_GICD_IRM_742_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_742_LEN    8
#define GICD_REGS_GICD_AFFINITY2_742_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_742_LEN    8
#define GICD_REGS_GICD_AFFINITY1_742_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_742_LEN    8
#define GICD_REGS_GICD_AFFINITY0_742_OFFSET 0

#define GICD_REGS_GICD_IRM_743_LEN          1
#define GICD_REGS_GICD_IRM_743_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_743_LEN    8
#define GICD_REGS_GICD_AFFINITY2_743_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_743_LEN    8
#define GICD_REGS_GICD_AFFINITY1_743_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_743_LEN    8
#define GICD_REGS_GICD_AFFINITY0_743_OFFSET 0

#define GICD_REGS_GICD_IRM_744_LEN          1
#define GICD_REGS_GICD_IRM_744_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_744_LEN    8
#define GICD_REGS_GICD_AFFINITY2_744_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_744_LEN    8
#define GICD_REGS_GICD_AFFINITY1_744_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_744_LEN    8
#define GICD_REGS_GICD_AFFINITY0_744_OFFSET 0

#define GICD_REGS_GICD_IRM_745_LEN          1
#define GICD_REGS_GICD_IRM_745_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_745_LEN    8
#define GICD_REGS_GICD_AFFINITY2_745_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_745_LEN    8
#define GICD_REGS_GICD_AFFINITY1_745_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_745_LEN    8
#define GICD_REGS_GICD_AFFINITY0_745_OFFSET 0

#define GICD_REGS_GICD_IRM_746_LEN          1
#define GICD_REGS_GICD_IRM_746_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_746_LEN    8
#define GICD_REGS_GICD_AFFINITY2_746_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_746_LEN    8
#define GICD_REGS_GICD_AFFINITY1_746_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_746_LEN    8
#define GICD_REGS_GICD_AFFINITY0_746_OFFSET 0

#define GICD_REGS_GICD_IRM_747_LEN          1
#define GICD_REGS_GICD_IRM_747_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_747_LEN    8
#define GICD_REGS_GICD_AFFINITY2_747_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_747_LEN    8
#define GICD_REGS_GICD_AFFINITY1_747_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_747_LEN    8
#define GICD_REGS_GICD_AFFINITY0_747_OFFSET 0

#define GICD_REGS_GICD_IRM_748_LEN          1
#define GICD_REGS_GICD_IRM_748_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_748_LEN    8
#define GICD_REGS_GICD_AFFINITY2_748_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_748_LEN    8
#define GICD_REGS_GICD_AFFINITY1_748_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_748_LEN    8
#define GICD_REGS_GICD_AFFINITY0_748_OFFSET 0

#define GICD_REGS_GICD_IRM_749_LEN          1
#define GICD_REGS_GICD_IRM_749_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_749_LEN    8
#define GICD_REGS_GICD_AFFINITY2_749_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_749_LEN    8
#define GICD_REGS_GICD_AFFINITY1_749_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_749_LEN    8
#define GICD_REGS_GICD_AFFINITY0_749_OFFSET 0

#define GICD_REGS_GICD_IRM_750_LEN          1
#define GICD_REGS_GICD_IRM_750_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_750_LEN    8
#define GICD_REGS_GICD_AFFINITY2_750_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_750_LEN    8
#define GICD_REGS_GICD_AFFINITY1_750_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_750_LEN    8
#define GICD_REGS_GICD_AFFINITY0_750_OFFSET 0

#define GICD_REGS_GICD_IRM_751_LEN          1
#define GICD_REGS_GICD_IRM_751_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_751_LEN    8
#define GICD_REGS_GICD_AFFINITY2_751_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_751_LEN    8
#define GICD_REGS_GICD_AFFINITY1_751_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_751_LEN    8
#define GICD_REGS_GICD_AFFINITY0_751_OFFSET 0

#define GICD_REGS_GICD_IRM_752_LEN          1
#define GICD_REGS_GICD_IRM_752_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_752_LEN    8
#define GICD_REGS_GICD_AFFINITY2_752_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_752_LEN    8
#define GICD_REGS_GICD_AFFINITY1_752_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_752_LEN    8
#define GICD_REGS_GICD_AFFINITY0_752_OFFSET 0

#define GICD_REGS_GICD_IRM_753_LEN          1
#define GICD_REGS_GICD_IRM_753_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_753_LEN    8
#define GICD_REGS_GICD_AFFINITY2_753_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_753_LEN    8
#define GICD_REGS_GICD_AFFINITY1_753_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_753_LEN    8
#define GICD_REGS_GICD_AFFINITY0_753_OFFSET 0

#define GICD_REGS_GICD_IRM_754_LEN          1
#define GICD_REGS_GICD_IRM_754_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_754_LEN    8
#define GICD_REGS_GICD_AFFINITY2_754_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_754_LEN    8
#define GICD_REGS_GICD_AFFINITY1_754_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_754_LEN    8
#define GICD_REGS_GICD_AFFINITY0_754_OFFSET 0

#define GICD_REGS_GICD_IRM_755_LEN          1
#define GICD_REGS_GICD_IRM_755_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_755_LEN    8
#define GICD_REGS_GICD_AFFINITY2_755_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_755_LEN    8
#define GICD_REGS_GICD_AFFINITY1_755_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_755_LEN    8
#define GICD_REGS_GICD_AFFINITY0_755_OFFSET 0

#define GICD_REGS_GICD_IRM_756_LEN          1
#define GICD_REGS_GICD_IRM_756_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_756_LEN    8
#define GICD_REGS_GICD_AFFINITY2_756_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_756_LEN    8
#define GICD_REGS_GICD_AFFINITY1_756_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_756_LEN    8
#define GICD_REGS_GICD_AFFINITY0_756_OFFSET 0

#define GICD_REGS_GICD_IRM_757_LEN          1
#define GICD_REGS_GICD_IRM_757_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_757_LEN    8
#define GICD_REGS_GICD_AFFINITY2_757_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_757_LEN    8
#define GICD_REGS_GICD_AFFINITY1_757_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_757_LEN    8
#define GICD_REGS_GICD_AFFINITY0_757_OFFSET 0

#define GICD_REGS_GICD_IRM_758_LEN          1
#define GICD_REGS_GICD_IRM_758_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_758_LEN    8
#define GICD_REGS_GICD_AFFINITY2_758_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_758_LEN    8
#define GICD_REGS_GICD_AFFINITY1_758_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_758_LEN    8
#define GICD_REGS_GICD_AFFINITY0_758_OFFSET 0

#define GICD_REGS_GICD_IRM_759_LEN          1
#define GICD_REGS_GICD_IRM_759_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_759_LEN    8
#define GICD_REGS_GICD_AFFINITY2_759_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_759_LEN    8
#define GICD_REGS_GICD_AFFINITY1_759_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_759_LEN    8
#define GICD_REGS_GICD_AFFINITY0_759_OFFSET 0

#define GICD_REGS_GICD_IRM_760_LEN          1
#define GICD_REGS_GICD_IRM_760_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_760_LEN    8
#define GICD_REGS_GICD_AFFINITY2_760_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_760_LEN    8
#define GICD_REGS_GICD_AFFINITY1_760_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_760_LEN    8
#define GICD_REGS_GICD_AFFINITY0_760_OFFSET 0

#define GICD_REGS_GICD_IRM_761_LEN          1
#define GICD_REGS_GICD_IRM_761_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_761_LEN    8
#define GICD_REGS_GICD_AFFINITY2_761_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_761_LEN    8
#define GICD_REGS_GICD_AFFINITY1_761_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_761_LEN    8
#define GICD_REGS_GICD_AFFINITY0_761_OFFSET 0

#define GICD_REGS_GICD_IRM_762_LEN          1
#define GICD_REGS_GICD_IRM_762_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_762_LEN    8
#define GICD_REGS_GICD_AFFINITY2_762_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_762_LEN    8
#define GICD_REGS_GICD_AFFINITY1_762_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_762_LEN    8
#define GICD_REGS_GICD_AFFINITY0_762_OFFSET 0

#define GICD_REGS_GICD_IRM_763_LEN          1
#define GICD_REGS_GICD_IRM_763_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_763_LEN    8
#define GICD_REGS_GICD_AFFINITY2_763_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_763_LEN    8
#define GICD_REGS_GICD_AFFINITY1_763_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_763_LEN    8
#define GICD_REGS_GICD_AFFINITY0_763_OFFSET 0

#define GICD_REGS_GICD_IRM_764_LEN          1
#define GICD_REGS_GICD_IRM_764_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_764_LEN    8
#define GICD_REGS_GICD_AFFINITY2_764_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_764_LEN    8
#define GICD_REGS_GICD_AFFINITY1_764_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_764_LEN    8
#define GICD_REGS_GICD_AFFINITY0_764_OFFSET 0

#define GICD_REGS_GICD_IRM_765_LEN          1
#define GICD_REGS_GICD_IRM_765_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_765_LEN    8
#define GICD_REGS_GICD_AFFINITY2_765_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_765_LEN    8
#define GICD_REGS_GICD_AFFINITY1_765_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_765_LEN    8
#define GICD_REGS_GICD_AFFINITY0_765_OFFSET 0

#define GICD_REGS_GICD_IRM_766_LEN          1
#define GICD_REGS_GICD_IRM_766_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_766_LEN    8
#define GICD_REGS_GICD_AFFINITY2_766_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_766_LEN    8
#define GICD_REGS_GICD_AFFINITY1_766_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_766_LEN    8
#define GICD_REGS_GICD_AFFINITY0_766_OFFSET 0

#define GICD_REGS_GICD_IRM_767_LEN          1
#define GICD_REGS_GICD_IRM_767_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_767_LEN    8
#define GICD_REGS_GICD_AFFINITY2_767_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_767_LEN    8
#define GICD_REGS_GICD_AFFINITY1_767_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_767_LEN    8
#define GICD_REGS_GICD_AFFINITY0_767_OFFSET 0

#define GICD_REGS_GICD_IRM_768_LEN          1
#define GICD_REGS_GICD_IRM_768_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_768_LEN    8
#define GICD_REGS_GICD_AFFINITY2_768_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_768_LEN    8
#define GICD_REGS_GICD_AFFINITY1_768_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_768_LEN    8
#define GICD_REGS_GICD_AFFINITY0_768_OFFSET 0

#define GICD_REGS_GICD_IRM_769_LEN          1
#define GICD_REGS_GICD_IRM_769_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_769_LEN    8
#define GICD_REGS_GICD_AFFINITY2_769_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_769_LEN    8
#define GICD_REGS_GICD_AFFINITY1_769_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_769_LEN    8
#define GICD_REGS_GICD_AFFINITY0_769_OFFSET 0

#define GICD_REGS_GICD_IRM_770_LEN          1
#define GICD_REGS_GICD_IRM_770_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_770_LEN    8
#define GICD_REGS_GICD_AFFINITY2_770_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_770_LEN    8
#define GICD_REGS_GICD_AFFINITY1_770_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_770_LEN    8
#define GICD_REGS_GICD_AFFINITY0_770_OFFSET 0

#define GICD_REGS_GICD_IRM_771_LEN          1
#define GICD_REGS_GICD_IRM_771_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_771_LEN    8
#define GICD_REGS_GICD_AFFINITY2_771_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_771_LEN    8
#define GICD_REGS_GICD_AFFINITY1_771_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_771_LEN    8
#define GICD_REGS_GICD_AFFINITY0_771_OFFSET 0

#define GICD_REGS_GICD_IRM_772_LEN          1
#define GICD_REGS_GICD_IRM_772_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_772_LEN    8
#define GICD_REGS_GICD_AFFINITY2_772_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_772_LEN    8
#define GICD_REGS_GICD_AFFINITY1_772_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_772_LEN    8
#define GICD_REGS_GICD_AFFINITY0_772_OFFSET 0

#define GICD_REGS_GICD_IRM_773_LEN          1
#define GICD_REGS_GICD_IRM_773_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_773_LEN    8
#define GICD_REGS_GICD_AFFINITY2_773_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_773_LEN    8
#define GICD_REGS_GICD_AFFINITY1_773_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_773_LEN    8
#define GICD_REGS_GICD_AFFINITY0_773_OFFSET 0

#define GICD_REGS_GICD_IRM_774_LEN          1
#define GICD_REGS_GICD_IRM_774_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_774_LEN    8
#define GICD_REGS_GICD_AFFINITY2_774_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_774_LEN    8
#define GICD_REGS_GICD_AFFINITY1_774_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_774_LEN    8
#define GICD_REGS_GICD_AFFINITY0_774_OFFSET 0

#define GICD_REGS_GICD_IRM_775_LEN          1
#define GICD_REGS_GICD_IRM_775_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_775_LEN    8
#define GICD_REGS_GICD_AFFINITY2_775_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_775_LEN    8
#define GICD_REGS_GICD_AFFINITY1_775_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_775_LEN    8
#define GICD_REGS_GICD_AFFINITY0_775_OFFSET 0

#define GICD_REGS_GICD_IRM_776_LEN          1
#define GICD_REGS_GICD_IRM_776_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_776_LEN    8
#define GICD_REGS_GICD_AFFINITY2_776_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_776_LEN    8
#define GICD_REGS_GICD_AFFINITY1_776_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_776_LEN    8
#define GICD_REGS_GICD_AFFINITY0_776_OFFSET 0

#define GICD_REGS_GICD_IRM_777_LEN          1
#define GICD_REGS_GICD_IRM_777_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_777_LEN    8
#define GICD_REGS_GICD_AFFINITY2_777_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_777_LEN    8
#define GICD_REGS_GICD_AFFINITY1_777_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_777_LEN    8
#define GICD_REGS_GICD_AFFINITY0_777_OFFSET 0

#define GICD_REGS_GICD_IRM_778_LEN          1
#define GICD_REGS_GICD_IRM_778_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_778_LEN    8
#define GICD_REGS_GICD_AFFINITY2_778_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_778_LEN    8
#define GICD_REGS_GICD_AFFINITY1_778_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_778_LEN    8
#define GICD_REGS_GICD_AFFINITY0_778_OFFSET 0

#define GICD_REGS_GICD_IRM_779_LEN          1
#define GICD_REGS_GICD_IRM_779_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_779_LEN    8
#define GICD_REGS_GICD_AFFINITY2_779_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_779_LEN    8
#define GICD_REGS_GICD_AFFINITY1_779_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_779_LEN    8
#define GICD_REGS_GICD_AFFINITY0_779_OFFSET 0

#define GICD_REGS_GICD_IRM_780_LEN          1
#define GICD_REGS_GICD_IRM_780_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_780_LEN    8
#define GICD_REGS_GICD_AFFINITY2_780_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_780_LEN    8
#define GICD_REGS_GICD_AFFINITY1_780_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_780_LEN    8
#define GICD_REGS_GICD_AFFINITY0_780_OFFSET 0

#define GICD_REGS_GICD_IRM_781_LEN          1
#define GICD_REGS_GICD_IRM_781_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_781_LEN    8
#define GICD_REGS_GICD_AFFINITY2_781_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_781_LEN    8
#define GICD_REGS_GICD_AFFINITY1_781_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_781_LEN    8
#define GICD_REGS_GICD_AFFINITY0_781_OFFSET 0

#define GICD_REGS_GICD_IRM_782_LEN          1
#define GICD_REGS_GICD_IRM_782_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_782_LEN    8
#define GICD_REGS_GICD_AFFINITY2_782_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_782_LEN    8
#define GICD_REGS_GICD_AFFINITY1_782_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_782_LEN    8
#define GICD_REGS_GICD_AFFINITY0_782_OFFSET 0

#define GICD_REGS_GICD_IRM_783_LEN          1
#define GICD_REGS_GICD_IRM_783_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_783_LEN    8
#define GICD_REGS_GICD_AFFINITY2_783_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_783_LEN    8
#define GICD_REGS_GICD_AFFINITY1_783_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_783_LEN    8
#define GICD_REGS_GICD_AFFINITY0_783_OFFSET 0

#define GICD_REGS_GICD_IRM_784_LEN          1
#define GICD_REGS_GICD_IRM_784_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_784_LEN    8
#define GICD_REGS_GICD_AFFINITY2_784_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_784_LEN    8
#define GICD_REGS_GICD_AFFINITY1_784_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_784_LEN    8
#define GICD_REGS_GICD_AFFINITY0_784_OFFSET 0

#define GICD_REGS_GICD_IRM_785_LEN          1
#define GICD_REGS_GICD_IRM_785_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_785_LEN    8
#define GICD_REGS_GICD_AFFINITY2_785_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_785_LEN    8
#define GICD_REGS_GICD_AFFINITY1_785_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_785_LEN    8
#define GICD_REGS_GICD_AFFINITY0_785_OFFSET 0

#define GICD_REGS_GICD_IRM_786_LEN          1
#define GICD_REGS_GICD_IRM_786_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_786_LEN    8
#define GICD_REGS_GICD_AFFINITY2_786_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_786_LEN    8
#define GICD_REGS_GICD_AFFINITY1_786_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_786_LEN    8
#define GICD_REGS_GICD_AFFINITY0_786_OFFSET 0

#define GICD_REGS_GICD_IRM_787_LEN          1
#define GICD_REGS_GICD_IRM_787_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_787_LEN    8
#define GICD_REGS_GICD_AFFINITY2_787_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_787_LEN    8
#define GICD_REGS_GICD_AFFINITY1_787_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_787_LEN    8
#define GICD_REGS_GICD_AFFINITY0_787_OFFSET 0

#define GICD_REGS_GICD_IRM_788_LEN          1
#define GICD_REGS_GICD_IRM_788_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_788_LEN    8
#define GICD_REGS_GICD_AFFINITY2_788_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_788_LEN    8
#define GICD_REGS_GICD_AFFINITY1_788_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_788_LEN    8
#define GICD_REGS_GICD_AFFINITY0_788_OFFSET 0

#define GICD_REGS_GICD_IRM_789_LEN          1
#define GICD_REGS_GICD_IRM_789_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_789_LEN    8
#define GICD_REGS_GICD_AFFINITY2_789_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_789_LEN    8
#define GICD_REGS_GICD_AFFINITY1_789_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_789_LEN    8
#define GICD_REGS_GICD_AFFINITY0_789_OFFSET 0

#define GICD_REGS_GICD_IRM_790_LEN          1
#define GICD_REGS_GICD_IRM_790_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_790_LEN    8
#define GICD_REGS_GICD_AFFINITY2_790_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_790_LEN    8
#define GICD_REGS_GICD_AFFINITY1_790_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_790_LEN    8
#define GICD_REGS_GICD_AFFINITY0_790_OFFSET 0

#define GICD_REGS_GICD_IRM_791_LEN          1
#define GICD_REGS_GICD_IRM_791_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_791_LEN    8
#define GICD_REGS_GICD_AFFINITY2_791_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_791_LEN    8
#define GICD_REGS_GICD_AFFINITY1_791_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_791_LEN    8
#define GICD_REGS_GICD_AFFINITY0_791_OFFSET 0

#define GICD_REGS_GICD_IRM_792_LEN          1
#define GICD_REGS_GICD_IRM_792_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_792_LEN    8
#define GICD_REGS_GICD_AFFINITY2_792_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_792_LEN    8
#define GICD_REGS_GICD_AFFINITY1_792_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_792_LEN    8
#define GICD_REGS_GICD_AFFINITY0_792_OFFSET 0

#define GICD_REGS_GICD_IRM_793_LEN          1
#define GICD_REGS_GICD_IRM_793_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_793_LEN    8
#define GICD_REGS_GICD_AFFINITY2_793_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_793_LEN    8
#define GICD_REGS_GICD_AFFINITY1_793_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_793_LEN    8
#define GICD_REGS_GICD_AFFINITY0_793_OFFSET 0

#define GICD_REGS_GICD_IRM_794_LEN          1
#define GICD_REGS_GICD_IRM_794_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_794_LEN    8
#define GICD_REGS_GICD_AFFINITY2_794_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_794_LEN    8
#define GICD_REGS_GICD_AFFINITY1_794_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_794_LEN    8
#define GICD_REGS_GICD_AFFINITY0_794_OFFSET 0

#define GICD_REGS_GICD_IRM_795_LEN          1
#define GICD_REGS_GICD_IRM_795_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_795_LEN    8
#define GICD_REGS_GICD_AFFINITY2_795_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_795_LEN    8
#define GICD_REGS_GICD_AFFINITY1_795_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_795_LEN    8
#define GICD_REGS_GICD_AFFINITY0_795_OFFSET 0

#define GICD_REGS_GICD_IRM_796_LEN          1
#define GICD_REGS_GICD_IRM_796_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_796_LEN    8
#define GICD_REGS_GICD_AFFINITY2_796_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_796_LEN    8
#define GICD_REGS_GICD_AFFINITY1_796_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_796_LEN    8
#define GICD_REGS_GICD_AFFINITY0_796_OFFSET 0

#define GICD_REGS_GICD_IRM_797_LEN          1
#define GICD_REGS_GICD_IRM_797_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_797_LEN    8
#define GICD_REGS_GICD_AFFINITY2_797_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_797_LEN    8
#define GICD_REGS_GICD_AFFINITY1_797_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_797_LEN    8
#define GICD_REGS_GICD_AFFINITY0_797_OFFSET 0

#define GICD_REGS_GICD_IRM_798_LEN          1
#define GICD_REGS_GICD_IRM_798_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_798_LEN    8
#define GICD_REGS_GICD_AFFINITY2_798_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_798_LEN    8
#define GICD_REGS_GICD_AFFINITY1_798_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_798_LEN    8
#define GICD_REGS_GICD_AFFINITY0_798_OFFSET 0

#define GICD_REGS_GICD_IRM_799_LEN          1
#define GICD_REGS_GICD_IRM_799_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_799_LEN    8
#define GICD_REGS_GICD_AFFINITY2_799_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_799_LEN    8
#define GICD_REGS_GICD_AFFINITY1_799_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_799_LEN    8
#define GICD_REGS_GICD_AFFINITY0_799_OFFSET 0

#define GICD_REGS_GICD_IRM_800_LEN          1
#define GICD_REGS_GICD_IRM_800_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_800_LEN    8
#define GICD_REGS_GICD_AFFINITY2_800_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_800_LEN    8
#define GICD_REGS_GICD_AFFINITY1_800_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_800_LEN    8
#define GICD_REGS_GICD_AFFINITY0_800_OFFSET 0

#define GICD_REGS_GICD_IRM_801_LEN          1
#define GICD_REGS_GICD_IRM_801_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_801_LEN    8
#define GICD_REGS_GICD_AFFINITY2_801_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_801_LEN    8
#define GICD_REGS_GICD_AFFINITY1_801_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_801_LEN    8
#define GICD_REGS_GICD_AFFINITY0_801_OFFSET 0

#define GICD_REGS_GICD_IRM_802_LEN          1
#define GICD_REGS_GICD_IRM_802_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_802_LEN    8
#define GICD_REGS_GICD_AFFINITY2_802_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_802_LEN    8
#define GICD_REGS_GICD_AFFINITY1_802_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_802_LEN    8
#define GICD_REGS_GICD_AFFINITY0_802_OFFSET 0

#define GICD_REGS_GICD_IRM_803_LEN          1
#define GICD_REGS_GICD_IRM_803_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_803_LEN    8
#define GICD_REGS_GICD_AFFINITY2_803_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_803_LEN    8
#define GICD_REGS_GICD_AFFINITY1_803_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_803_LEN    8
#define GICD_REGS_GICD_AFFINITY0_803_OFFSET 0

#define GICD_REGS_GICD_IRM_804_LEN          1
#define GICD_REGS_GICD_IRM_804_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_804_LEN    8
#define GICD_REGS_GICD_AFFINITY2_804_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_804_LEN    8
#define GICD_REGS_GICD_AFFINITY1_804_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_804_LEN    8
#define GICD_REGS_GICD_AFFINITY0_804_OFFSET 0

#define GICD_REGS_GICD_IRM_805_LEN          1
#define GICD_REGS_GICD_IRM_805_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_805_LEN    8
#define GICD_REGS_GICD_AFFINITY2_805_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_805_LEN    8
#define GICD_REGS_GICD_AFFINITY1_805_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_805_LEN    8
#define GICD_REGS_GICD_AFFINITY0_805_OFFSET 0

#define GICD_REGS_GICD_IRM_806_LEN          1
#define GICD_REGS_GICD_IRM_806_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_806_LEN    8
#define GICD_REGS_GICD_AFFINITY2_806_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_806_LEN    8
#define GICD_REGS_GICD_AFFINITY1_806_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_806_LEN    8
#define GICD_REGS_GICD_AFFINITY0_806_OFFSET 0

#define GICD_REGS_GICD_IRM_807_LEN          1
#define GICD_REGS_GICD_IRM_807_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_807_LEN    8
#define GICD_REGS_GICD_AFFINITY2_807_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_807_LEN    8
#define GICD_REGS_GICD_AFFINITY1_807_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_807_LEN    8
#define GICD_REGS_GICD_AFFINITY0_807_OFFSET 0

#define GICD_REGS_GICD_IRM_808_LEN          1
#define GICD_REGS_GICD_IRM_808_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_808_LEN    8
#define GICD_REGS_GICD_AFFINITY2_808_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_808_LEN    8
#define GICD_REGS_GICD_AFFINITY1_808_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_808_LEN    8
#define GICD_REGS_GICD_AFFINITY0_808_OFFSET 0

#define GICD_REGS_GICD_IRM_809_LEN          1
#define GICD_REGS_GICD_IRM_809_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_809_LEN    8
#define GICD_REGS_GICD_AFFINITY2_809_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_809_LEN    8
#define GICD_REGS_GICD_AFFINITY1_809_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_809_LEN    8
#define GICD_REGS_GICD_AFFINITY0_809_OFFSET 0

#define GICD_REGS_GICD_IRM_810_LEN          1
#define GICD_REGS_GICD_IRM_810_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_810_LEN    8
#define GICD_REGS_GICD_AFFINITY2_810_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_810_LEN    8
#define GICD_REGS_GICD_AFFINITY1_810_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_810_LEN    8
#define GICD_REGS_GICD_AFFINITY0_810_OFFSET 0

#define GICD_REGS_GICD_IRM_811_LEN          1
#define GICD_REGS_GICD_IRM_811_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_811_LEN    8
#define GICD_REGS_GICD_AFFINITY2_811_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_811_LEN    8
#define GICD_REGS_GICD_AFFINITY1_811_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_811_LEN    8
#define GICD_REGS_GICD_AFFINITY0_811_OFFSET 0

#define GICD_REGS_GICD_IRM_812_LEN          1
#define GICD_REGS_GICD_IRM_812_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_812_LEN    8
#define GICD_REGS_GICD_AFFINITY2_812_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_812_LEN    8
#define GICD_REGS_GICD_AFFINITY1_812_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_812_LEN    8
#define GICD_REGS_GICD_AFFINITY0_812_OFFSET 0

#define GICD_REGS_GICD_IRM_813_LEN          1
#define GICD_REGS_GICD_IRM_813_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_813_LEN    8
#define GICD_REGS_GICD_AFFINITY2_813_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_813_LEN    8
#define GICD_REGS_GICD_AFFINITY1_813_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_813_LEN    8
#define GICD_REGS_GICD_AFFINITY0_813_OFFSET 0

#define GICD_REGS_GICD_IRM_814_LEN          1
#define GICD_REGS_GICD_IRM_814_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_814_LEN    8
#define GICD_REGS_GICD_AFFINITY2_814_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_814_LEN    8
#define GICD_REGS_GICD_AFFINITY1_814_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_814_LEN    8
#define GICD_REGS_GICD_AFFINITY0_814_OFFSET 0

#define GICD_REGS_GICD_IRM_815_LEN          1
#define GICD_REGS_GICD_IRM_815_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_815_LEN    8
#define GICD_REGS_GICD_AFFINITY2_815_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_815_LEN    8
#define GICD_REGS_GICD_AFFINITY1_815_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_815_LEN    8
#define GICD_REGS_GICD_AFFINITY0_815_OFFSET 0

#define GICD_REGS_GICD_IRM_816_LEN          1
#define GICD_REGS_GICD_IRM_816_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_816_LEN    8
#define GICD_REGS_GICD_AFFINITY2_816_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_816_LEN    8
#define GICD_REGS_GICD_AFFINITY1_816_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_816_LEN    8
#define GICD_REGS_GICD_AFFINITY0_816_OFFSET 0

#define GICD_REGS_GICD_IRM_817_LEN          1
#define GICD_REGS_GICD_IRM_817_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_817_LEN    8
#define GICD_REGS_GICD_AFFINITY2_817_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_817_LEN    8
#define GICD_REGS_GICD_AFFINITY1_817_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_817_LEN    8
#define GICD_REGS_GICD_AFFINITY0_817_OFFSET 0

#define GICD_REGS_GICD_IRM_818_LEN          1
#define GICD_REGS_GICD_IRM_818_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_818_LEN    8
#define GICD_REGS_GICD_AFFINITY2_818_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_818_LEN    8
#define GICD_REGS_GICD_AFFINITY1_818_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_818_LEN    8
#define GICD_REGS_GICD_AFFINITY0_818_OFFSET 0

#define GICD_REGS_GICD_IRM_819_LEN          1
#define GICD_REGS_GICD_IRM_819_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_819_LEN    8
#define GICD_REGS_GICD_AFFINITY2_819_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_819_LEN    8
#define GICD_REGS_GICD_AFFINITY1_819_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_819_LEN    8
#define GICD_REGS_GICD_AFFINITY0_819_OFFSET 0

#define GICD_REGS_GICD_IRM_820_LEN          1
#define GICD_REGS_GICD_IRM_820_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_820_LEN    8
#define GICD_REGS_GICD_AFFINITY2_820_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_820_LEN    8
#define GICD_REGS_GICD_AFFINITY1_820_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_820_LEN    8
#define GICD_REGS_GICD_AFFINITY0_820_OFFSET 0

#define GICD_REGS_GICD_IRM_821_LEN          1
#define GICD_REGS_GICD_IRM_821_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_821_LEN    8
#define GICD_REGS_GICD_AFFINITY2_821_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_821_LEN    8
#define GICD_REGS_GICD_AFFINITY1_821_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_821_LEN    8
#define GICD_REGS_GICD_AFFINITY0_821_OFFSET 0

#define GICD_REGS_GICD_IRM_822_LEN          1
#define GICD_REGS_GICD_IRM_822_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_822_LEN    8
#define GICD_REGS_GICD_AFFINITY2_822_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_822_LEN    8
#define GICD_REGS_GICD_AFFINITY1_822_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_822_LEN    8
#define GICD_REGS_GICD_AFFINITY0_822_OFFSET 0

#define GICD_REGS_GICD_IRM_823_LEN          1
#define GICD_REGS_GICD_IRM_823_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_823_LEN    8
#define GICD_REGS_GICD_AFFINITY2_823_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_823_LEN    8
#define GICD_REGS_GICD_AFFINITY1_823_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_823_LEN    8
#define GICD_REGS_GICD_AFFINITY0_823_OFFSET 0

#define GICD_REGS_GICD_IRM_824_LEN          1
#define GICD_REGS_GICD_IRM_824_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_824_LEN    8
#define GICD_REGS_GICD_AFFINITY2_824_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_824_LEN    8
#define GICD_REGS_GICD_AFFINITY1_824_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_824_LEN    8
#define GICD_REGS_GICD_AFFINITY0_824_OFFSET 0

#define GICD_REGS_GICD_IRM_825_LEN          1
#define GICD_REGS_GICD_IRM_825_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_825_LEN    8
#define GICD_REGS_GICD_AFFINITY2_825_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_825_LEN    8
#define GICD_REGS_GICD_AFFINITY1_825_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_825_LEN    8
#define GICD_REGS_GICD_AFFINITY0_825_OFFSET 0

#define GICD_REGS_GICD_IRM_826_LEN          1
#define GICD_REGS_GICD_IRM_826_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_826_LEN    8
#define GICD_REGS_GICD_AFFINITY2_826_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_826_LEN    8
#define GICD_REGS_GICD_AFFINITY1_826_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_826_LEN    8
#define GICD_REGS_GICD_AFFINITY0_826_OFFSET 0

#define GICD_REGS_GICD_IRM_827_LEN          1
#define GICD_REGS_GICD_IRM_827_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_827_LEN    8
#define GICD_REGS_GICD_AFFINITY2_827_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_827_LEN    8
#define GICD_REGS_GICD_AFFINITY1_827_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_827_LEN    8
#define GICD_REGS_GICD_AFFINITY0_827_OFFSET 0

#define GICD_REGS_GICD_IRM_828_LEN          1
#define GICD_REGS_GICD_IRM_828_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_828_LEN    8
#define GICD_REGS_GICD_AFFINITY2_828_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_828_LEN    8
#define GICD_REGS_GICD_AFFINITY1_828_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_828_LEN    8
#define GICD_REGS_GICD_AFFINITY0_828_OFFSET 0

#define GICD_REGS_GICD_IRM_829_LEN          1
#define GICD_REGS_GICD_IRM_829_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_829_LEN    8
#define GICD_REGS_GICD_AFFINITY2_829_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_829_LEN    8
#define GICD_REGS_GICD_AFFINITY1_829_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_829_LEN    8
#define GICD_REGS_GICD_AFFINITY0_829_OFFSET 0

#define GICD_REGS_GICD_IRM_830_LEN          1
#define GICD_REGS_GICD_IRM_830_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_830_LEN    8
#define GICD_REGS_GICD_AFFINITY2_830_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_830_LEN    8
#define GICD_REGS_GICD_AFFINITY1_830_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_830_LEN    8
#define GICD_REGS_GICD_AFFINITY0_830_OFFSET 0

#define GICD_REGS_GICD_IRM_831_LEN          1
#define GICD_REGS_GICD_IRM_831_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_831_LEN    8
#define GICD_REGS_GICD_AFFINITY2_831_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_831_LEN    8
#define GICD_REGS_GICD_AFFINITY1_831_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_831_LEN    8
#define GICD_REGS_GICD_AFFINITY0_831_OFFSET 0

#define GICD_REGS_GICD_IRM_832_LEN          1
#define GICD_REGS_GICD_IRM_832_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_832_LEN    8
#define GICD_REGS_GICD_AFFINITY2_832_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_832_LEN    8
#define GICD_REGS_GICD_AFFINITY1_832_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_832_LEN    8
#define GICD_REGS_GICD_AFFINITY0_832_OFFSET 0

#define GICD_REGS_GICD_IRM_833_LEN          1
#define GICD_REGS_GICD_IRM_833_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_833_LEN    8
#define GICD_REGS_GICD_AFFINITY2_833_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_833_LEN    8
#define GICD_REGS_GICD_AFFINITY1_833_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_833_LEN    8
#define GICD_REGS_GICD_AFFINITY0_833_OFFSET 0

#define GICD_REGS_GICD_IRM_834_LEN          1
#define GICD_REGS_GICD_IRM_834_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_834_LEN    8
#define GICD_REGS_GICD_AFFINITY2_834_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_834_LEN    8
#define GICD_REGS_GICD_AFFINITY1_834_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_834_LEN    8
#define GICD_REGS_GICD_AFFINITY0_834_OFFSET 0

#define GICD_REGS_GICD_IRM_835_LEN          1
#define GICD_REGS_GICD_IRM_835_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_835_LEN    8
#define GICD_REGS_GICD_AFFINITY2_835_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_835_LEN    8
#define GICD_REGS_GICD_AFFINITY1_835_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_835_LEN    8
#define GICD_REGS_GICD_AFFINITY0_835_OFFSET 0

#define GICD_REGS_GICD_IRM_836_LEN          1
#define GICD_REGS_GICD_IRM_836_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_836_LEN    8
#define GICD_REGS_GICD_AFFINITY2_836_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_836_LEN    8
#define GICD_REGS_GICD_AFFINITY1_836_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_836_LEN    8
#define GICD_REGS_GICD_AFFINITY0_836_OFFSET 0

#define GICD_REGS_GICD_IRM_837_LEN          1
#define GICD_REGS_GICD_IRM_837_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_837_LEN    8
#define GICD_REGS_GICD_AFFINITY2_837_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_837_LEN    8
#define GICD_REGS_GICD_AFFINITY1_837_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_837_LEN    8
#define GICD_REGS_GICD_AFFINITY0_837_OFFSET 0

#define GICD_REGS_GICD_IRM_838_LEN          1
#define GICD_REGS_GICD_IRM_838_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_838_LEN    8
#define GICD_REGS_GICD_AFFINITY2_838_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_838_LEN    8
#define GICD_REGS_GICD_AFFINITY1_838_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_838_LEN    8
#define GICD_REGS_GICD_AFFINITY0_838_OFFSET 0

#define GICD_REGS_GICD_IRM_839_LEN          1
#define GICD_REGS_GICD_IRM_839_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_839_LEN    8
#define GICD_REGS_GICD_AFFINITY2_839_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_839_LEN    8
#define GICD_REGS_GICD_AFFINITY1_839_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_839_LEN    8
#define GICD_REGS_GICD_AFFINITY0_839_OFFSET 0

#define GICD_REGS_GICD_IRM_840_LEN          1
#define GICD_REGS_GICD_IRM_840_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_840_LEN    8
#define GICD_REGS_GICD_AFFINITY2_840_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_840_LEN    8
#define GICD_REGS_GICD_AFFINITY1_840_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_840_LEN    8
#define GICD_REGS_GICD_AFFINITY0_840_OFFSET 0

#define GICD_REGS_GICD_IRM_841_LEN          1
#define GICD_REGS_GICD_IRM_841_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_841_LEN    8
#define GICD_REGS_GICD_AFFINITY2_841_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_841_LEN    8
#define GICD_REGS_GICD_AFFINITY1_841_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_841_LEN    8
#define GICD_REGS_GICD_AFFINITY0_841_OFFSET 0

#define GICD_REGS_GICD_IRM_842_LEN          1
#define GICD_REGS_GICD_IRM_842_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_842_LEN    8
#define GICD_REGS_GICD_AFFINITY2_842_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_842_LEN    8
#define GICD_REGS_GICD_AFFINITY1_842_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_842_LEN    8
#define GICD_REGS_GICD_AFFINITY0_842_OFFSET 0

#define GICD_REGS_GICD_IRM_843_LEN          1
#define GICD_REGS_GICD_IRM_843_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_843_LEN    8
#define GICD_REGS_GICD_AFFINITY2_843_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_843_LEN    8
#define GICD_REGS_GICD_AFFINITY1_843_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_843_LEN    8
#define GICD_REGS_GICD_AFFINITY0_843_OFFSET 0

#define GICD_REGS_GICD_IRM_844_LEN          1
#define GICD_REGS_GICD_IRM_844_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_844_LEN    8
#define GICD_REGS_GICD_AFFINITY2_844_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_844_LEN    8
#define GICD_REGS_GICD_AFFINITY1_844_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_844_LEN    8
#define GICD_REGS_GICD_AFFINITY0_844_OFFSET 0

#define GICD_REGS_GICD_IRM_845_LEN          1
#define GICD_REGS_GICD_IRM_845_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_845_LEN    8
#define GICD_REGS_GICD_AFFINITY2_845_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_845_LEN    8
#define GICD_REGS_GICD_AFFINITY1_845_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_845_LEN    8
#define GICD_REGS_GICD_AFFINITY0_845_OFFSET 0

#define GICD_REGS_GICD_IRM_846_LEN          1
#define GICD_REGS_GICD_IRM_846_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_846_LEN    8
#define GICD_REGS_GICD_AFFINITY2_846_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_846_LEN    8
#define GICD_REGS_GICD_AFFINITY1_846_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_846_LEN    8
#define GICD_REGS_GICD_AFFINITY0_846_OFFSET 0

#define GICD_REGS_GICD_IRM_847_LEN          1
#define GICD_REGS_GICD_IRM_847_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_847_LEN    8
#define GICD_REGS_GICD_AFFINITY2_847_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_847_LEN    8
#define GICD_REGS_GICD_AFFINITY1_847_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_847_LEN    8
#define GICD_REGS_GICD_AFFINITY0_847_OFFSET 0

#define GICD_REGS_GICD_IRM_848_LEN          1
#define GICD_REGS_GICD_IRM_848_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_848_LEN    8
#define GICD_REGS_GICD_AFFINITY2_848_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_848_LEN    8
#define GICD_REGS_GICD_AFFINITY1_848_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_848_LEN    8
#define GICD_REGS_GICD_AFFINITY0_848_OFFSET 0

#define GICD_REGS_GICD_IRM_849_LEN          1
#define GICD_REGS_GICD_IRM_849_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_849_LEN    8
#define GICD_REGS_GICD_AFFINITY2_849_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_849_LEN    8
#define GICD_REGS_GICD_AFFINITY1_849_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_849_LEN    8
#define GICD_REGS_GICD_AFFINITY0_849_OFFSET 0

#define GICD_REGS_GICD_IRM_850_LEN          1
#define GICD_REGS_GICD_IRM_850_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_850_LEN    8
#define GICD_REGS_GICD_AFFINITY2_850_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_850_LEN    8
#define GICD_REGS_GICD_AFFINITY1_850_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_850_LEN    8
#define GICD_REGS_GICD_AFFINITY0_850_OFFSET 0

#define GICD_REGS_GICD_IRM_851_LEN          1
#define GICD_REGS_GICD_IRM_851_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_851_LEN    8
#define GICD_REGS_GICD_AFFINITY2_851_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_851_LEN    8
#define GICD_REGS_GICD_AFFINITY1_851_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_851_LEN    8
#define GICD_REGS_GICD_AFFINITY0_851_OFFSET 0

#define GICD_REGS_GICD_IRM_852_LEN          1
#define GICD_REGS_GICD_IRM_852_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_852_LEN    8
#define GICD_REGS_GICD_AFFINITY2_852_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_852_LEN    8
#define GICD_REGS_GICD_AFFINITY1_852_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_852_LEN    8
#define GICD_REGS_GICD_AFFINITY0_852_OFFSET 0

#define GICD_REGS_GICD_IRM_853_LEN          1
#define GICD_REGS_GICD_IRM_853_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_853_LEN    8
#define GICD_REGS_GICD_AFFINITY2_853_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_853_LEN    8
#define GICD_REGS_GICD_AFFINITY1_853_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_853_LEN    8
#define GICD_REGS_GICD_AFFINITY0_853_OFFSET 0

#define GICD_REGS_GICD_IRM_854_LEN          1
#define GICD_REGS_GICD_IRM_854_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_854_LEN    8
#define GICD_REGS_GICD_AFFINITY2_854_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_854_LEN    8
#define GICD_REGS_GICD_AFFINITY1_854_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_854_LEN    8
#define GICD_REGS_GICD_AFFINITY0_854_OFFSET 0

#define GICD_REGS_GICD_IRM_855_LEN          1
#define GICD_REGS_GICD_IRM_855_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_855_LEN    8
#define GICD_REGS_GICD_AFFINITY2_855_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_855_LEN    8
#define GICD_REGS_GICD_AFFINITY1_855_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_855_LEN    8
#define GICD_REGS_GICD_AFFINITY0_855_OFFSET 0

#define GICD_REGS_GICD_IRM_856_LEN          1
#define GICD_REGS_GICD_IRM_856_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_856_LEN    8
#define GICD_REGS_GICD_AFFINITY2_856_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_856_LEN    8
#define GICD_REGS_GICD_AFFINITY1_856_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_856_LEN    8
#define GICD_REGS_GICD_AFFINITY0_856_OFFSET 0

#define GICD_REGS_GICD_IRM_857_LEN          1
#define GICD_REGS_GICD_IRM_857_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_857_LEN    8
#define GICD_REGS_GICD_AFFINITY2_857_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_857_LEN    8
#define GICD_REGS_GICD_AFFINITY1_857_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_857_LEN    8
#define GICD_REGS_GICD_AFFINITY0_857_OFFSET 0

#define GICD_REGS_GICD_IRM_858_LEN          1
#define GICD_REGS_GICD_IRM_858_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_858_LEN    8
#define GICD_REGS_GICD_AFFINITY2_858_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_858_LEN    8
#define GICD_REGS_GICD_AFFINITY1_858_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_858_LEN    8
#define GICD_REGS_GICD_AFFINITY0_858_OFFSET 0

#define GICD_REGS_GICD_IRM_859_LEN          1
#define GICD_REGS_GICD_IRM_859_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_859_LEN    8
#define GICD_REGS_GICD_AFFINITY2_859_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_859_LEN    8
#define GICD_REGS_GICD_AFFINITY1_859_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_859_LEN    8
#define GICD_REGS_GICD_AFFINITY0_859_OFFSET 0

#define GICD_REGS_GICD_IRM_860_LEN          1
#define GICD_REGS_GICD_IRM_860_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_860_LEN    8
#define GICD_REGS_GICD_AFFINITY2_860_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_860_LEN    8
#define GICD_REGS_GICD_AFFINITY1_860_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_860_LEN    8
#define GICD_REGS_GICD_AFFINITY0_860_OFFSET 0

#define GICD_REGS_GICD_IRM_861_LEN          1
#define GICD_REGS_GICD_IRM_861_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_861_LEN    8
#define GICD_REGS_GICD_AFFINITY2_861_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_861_LEN    8
#define GICD_REGS_GICD_AFFINITY1_861_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_861_LEN    8
#define GICD_REGS_GICD_AFFINITY0_861_OFFSET 0

#define GICD_REGS_GICD_IRM_862_LEN          1
#define GICD_REGS_GICD_IRM_862_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_862_LEN    8
#define GICD_REGS_GICD_AFFINITY2_862_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_862_LEN    8
#define GICD_REGS_GICD_AFFINITY1_862_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_862_LEN    8
#define GICD_REGS_GICD_AFFINITY0_862_OFFSET 0

#define GICD_REGS_GICD_IRM_863_LEN          1
#define GICD_REGS_GICD_IRM_863_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_863_LEN    8
#define GICD_REGS_GICD_AFFINITY2_863_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_863_LEN    8
#define GICD_REGS_GICD_AFFINITY1_863_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_863_LEN    8
#define GICD_REGS_GICD_AFFINITY0_863_OFFSET 0

#define GICD_REGS_GICD_IRM_864_LEN          1
#define GICD_REGS_GICD_IRM_864_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_864_LEN    8
#define GICD_REGS_GICD_AFFINITY2_864_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_864_LEN    8
#define GICD_REGS_GICD_AFFINITY1_864_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_864_LEN    8
#define GICD_REGS_GICD_AFFINITY0_864_OFFSET 0

#define GICD_REGS_GICD_IRM_865_LEN          1
#define GICD_REGS_GICD_IRM_865_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_865_LEN    8
#define GICD_REGS_GICD_AFFINITY2_865_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_865_LEN    8
#define GICD_REGS_GICD_AFFINITY1_865_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_865_LEN    8
#define GICD_REGS_GICD_AFFINITY0_865_OFFSET 0

#define GICD_REGS_GICD_IRM_866_LEN          1
#define GICD_REGS_GICD_IRM_866_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_866_LEN    8
#define GICD_REGS_GICD_AFFINITY2_866_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_866_LEN    8
#define GICD_REGS_GICD_AFFINITY1_866_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_866_LEN    8
#define GICD_REGS_GICD_AFFINITY0_866_OFFSET 0

#define GICD_REGS_GICD_IRM_867_LEN          1
#define GICD_REGS_GICD_IRM_867_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_867_LEN    8
#define GICD_REGS_GICD_AFFINITY2_867_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_867_LEN    8
#define GICD_REGS_GICD_AFFINITY1_867_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_867_LEN    8
#define GICD_REGS_GICD_AFFINITY0_867_OFFSET 0

#define GICD_REGS_GICD_IRM_868_LEN          1
#define GICD_REGS_GICD_IRM_868_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_868_LEN    8
#define GICD_REGS_GICD_AFFINITY2_868_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_868_LEN    8
#define GICD_REGS_GICD_AFFINITY1_868_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_868_LEN    8
#define GICD_REGS_GICD_AFFINITY0_868_OFFSET 0

#define GICD_REGS_GICD_IRM_869_LEN          1
#define GICD_REGS_GICD_IRM_869_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_869_LEN    8
#define GICD_REGS_GICD_AFFINITY2_869_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_869_LEN    8
#define GICD_REGS_GICD_AFFINITY1_869_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_869_LEN    8
#define GICD_REGS_GICD_AFFINITY0_869_OFFSET 0

#define GICD_REGS_GICD_IRM_870_LEN          1
#define GICD_REGS_GICD_IRM_870_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_870_LEN    8
#define GICD_REGS_GICD_AFFINITY2_870_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_870_LEN    8
#define GICD_REGS_GICD_AFFINITY1_870_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_870_LEN    8
#define GICD_REGS_GICD_AFFINITY0_870_OFFSET 0

#define GICD_REGS_GICD_IRM_871_LEN          1
#define GICD_REGS_GICD_IRM_871_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_871_LEN    8
#define GICD_REGS_GICD_AFFINITY2_871_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_871_LEN    8
#define GICD_REGS_GICD_AFFINITY1_871_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_871_LEN    8
#define GICD_REGS_GICD_AFFINITY0_871_OFFSET 0

#define GICD_REGS_GICD_IRM_872_LEN          1
#define GICD_REGS_GICD_IRM_872_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_872_LEN    8
#define GICD_REGS_GICD_AFFINITY2_872_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_872_LEN    8
#define GICD_REGS_GICD_AFFINITY1_872_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_872_LEN    8
#define GICD_REGS_GICD_AFFINITY0_872_OFFSET 0

#define GICD_REGS_GICD_IRM_873_LEN          1
#define GICD_REGS_GICD_IRM_873_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_873_LEN    8
#define GICD_REGS_GICD_AFFINITY2_873_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_873_LEN    8
#define GICD_REGS_GICD_AFFINITY1_873_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_873_LEN    8
#define GICD_REGS_GICD_AFFINITY0_873_OFFSET 0

#define GICD_REGS_GICD_IRM_874_LEN          1
#define GICD_REGS_GICD_IRM_874_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_874_LEN    8
#define GICD_REGS_GICD_AFFINITY2_874_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_874_LEN    8
#define GICD_REGS_GICD_AFFINITY1_874_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_874_LEN    8
#define GICD_REGS_GICD_AFFINITY0_874_OFFSET 0

#define GICD_REGS_GICD_IRM_875_LEN          1
#define GICD_REGS_GICD_IRM_875_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_875_LEN    8
#define GICD_REGS_GICD_AFFINITY2_875_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_875_LEN    8
#define GICD_REGS_GICD_AFFINITY1_875_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_875_LEN    8
#define GICD_REGS_GICD_AFFINITY0_875_OFFSET 0

#define GICD_REGS_GICD_IRM_876_LEN          1
#define GICD_REGS_GICD_IRM_876_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_876_LEN    8
#define GICD_REGS_GICD_AFFINITY2_876_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_876_LEN    8
#define GICD_REGS_GICD_AFFINITY1_876_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_876_LEN    8
#define GICD_REGS_GICD_AFFINITY0_876_OFFSET 0

#define GICD_REGS_GICD_IRM_877_LEN          1
#define GICD_REGS_GICD_IRM_877_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_877_LEN    8
#define GICD_REGS_GICD_AFFINITY2_877_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_877_LEN    8
#define GICD_REGS_GICD_AFFINITY1_877_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_877_LEN    8
#define GICD_REGS_GICD_AFFINITY0_877_OFFSET 0

#define GICD_REGS_GICD_IRM_878_LEN          1
#define GICD_REGS_GICD_IRM_878_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_878_LEN    8
#define GICD_REGS_GICD_AFFINITY2_878_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_878_LEN    8
#define GICD_REGS_GICD_AFFINITY1_878_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_878_LEN    8
#define GICD_REGS_GICD_AFFINITY0_878_OFFSET 0

#define GICD_REGS_GICD_IRM_879_LEN          1
#define GICD_REGS_GICD_IRM_879_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_879_LEN    8
#define GICD_REGS_GICD_AFFINITY2_879_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_879_LEN    8
#define GICD_REGS_GICD_AFFINITY1_879_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_879_LEN    8
#define GICD_REGS_GICD_AFFINITY0_879_OFFSET 0

#define GICD_REGS_GICD_IRM_880_LEN          1
#define GICD_REGS_GICD_IRM_880_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_880_LEN    8
#define GICD_REGS_GICD_AFFINITY2_880_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_880_LEN    8
#define GICD_REGS_GICD_AFFINITY1_880_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_880_LEN    8
#define GICD_REGS_GICD_AFFINITY0_880_OFFSET 0

#define GICD_REGS_GICD_IRM_881_LEN          1
#define GICD_REGS_GICD_IRM_881_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_881_LEN    8
#define GICD_REGS_GICD_AFFINITY2_881_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_881_LEN    8
#define GICD_REGS_GICD_AFFINITY1_881_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_881_LEN    8
#define GICD_REGS_GICD_AFFINITY0_881_OFFSET 0

#define GICD_REGS_GICD_IRM_882_LEN          1
#define GICD_REGS_GICD_IRM_882_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_882_LEN    8
#define GICD_REGS_GICD_AFFINITY2_882_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_882_LEN    8
#define GICD_REGS_GICD_AFFINITY1_882_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_882_LEN    8
#define GICD_REGS_GICD_AFFINITY0_882_OFFSET 0

#define GICD_REGS_GICD_IRM_883_LEN          1
#define GICD_REGS_GICD_IRM_883_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_883_LEN    8
#define GICD_REGS_GICD_AFFINITY2_883_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_883_LEN    8
#define GICD_REGS_GICD_AFFINITY1_883_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_883_LEN    8
#define GICD_REGS_GICD_AFFINITY0_883_OFFSET 0

#define GICD_REGS_GICD_IRM_884_LEN          1
#define GICD_REGS_GICD_IRM_884_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_884_LEN    8
#define GICD_REGS_GICD_AFFINITY2_884_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_884_LEN    8
#define GICD_REGS_GICD_AFFINITY1_884_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_884_LEN    8
#define GICD_REGS_GICD_AFFINITY0_884_OFFSET 0

#define GICD_REGS_GICD_IRM_885_LEN          1
#define GICD_REGS_GICD_IRM_885_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_885_LEN    8
#define GICD_REGS_GICD_AFFINITY2_885_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_885_LEN    8
#define GICD_REGS_GICD_AFFINITY1_885_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_885_LEN    8
#define GICD_REGS_GICD_AFFINITY0_885_OFFSET 0

#define GICD_REGS_GICD_IRM_886_LEN          1
#define GICD_REGS_GICD_IRM_886_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_886_LEN    8
#define GICD_REGS_GICD_AFFINITY2_886_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_886_LEN    8
#define GICD_REGS_GICD_AFFINITY1_886_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_886_LEN    8
#define GICD_REGS_GICD_AFFINITY0_886_OFFSET 0

#define GICD_REGS_GICD_IRM_887_LEN          1
#define GICD_REGS_GICD_IRM_887_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_887_LEN    8
#define GICD_REGS_GICD_AFFINITY2_887_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_887_LEN    8
#define GICD_REGS_GICD_AFFINITY1_887_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_887_LEN    8
#define GICD_REGS_GICD_AFFINITY0_887_OFFSET 0

#define GICD_REGS_GICD_IRM_888_LEN          1
#define GICD_REGS_GICD_IRM_888_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_888_LEN    8
#define GICD_REGS_GICD_AFFINITY2_888_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_888_LEN    8
#define GICD_REGS_GICD_AFFINITY1_888_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_888_LEN    8
#define GICD_REGS_GICD_AFFINITY0_888_OFFSET 0

#define GICD_REGS_GICD_IRM_889_LEN          1
#define GICD_REGS_GICD_IRM_889_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_889_LEN    8
#define GICD_REGS_GICD_AFFINITY2_889_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_889_LEN    8
#define GICD_REGS_GICD_AFFINITY1_889_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_889_LEN    8
#define GICD_REGS_GICD_AFFINITY0_889_OFFSET 0

#define GICD_REGS_GICD_IRM_890_LEN          1
#define GICD_REGS_GICD_IRM_890_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_890_LEN    8
#define GICD_REGS_GICD_AFFINITY2_890_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_890_LEN    8
#define GICD_REGS_GICD_AFFINITY1_890_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_890_LEN    8
#define GICD_REGS_GICD_AFFINITY0_890_OFFSET 0

#define GICD_REGS_GICD_IRM_891_LEN          1
#define GICD_REGS_GICD_IRM_891_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_891_LEN    8
#define GICD_REGS_GICD_AFFINITY2_891_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_891_LEN    8
#define GICD_REGS_GICD_AFFINITY1_891_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_891_LEN    8
#define GICD_REGS_GICD_AFFINITY0_891_OFFSET 0

#define GICD_REGS_GICD_IRM_892_LEN          1
#define GICD_REGS_GICD_IRM_892_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_892_LEN    8
#define GICD_REGS_GICD_AFFINITY2_892_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_892_LEN    8
#define GICD_REGS_GICD_AFFINITY1_892_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_892_LEN    8
#define GICD_REGS_GICD_AFFINITY0_892_OFFSET 0

#define GICD_REGS_GICD_IRM_893_LEN          1
#define GICD_REGS_GICD_IRM_893_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_893_LEN    8
#define GICD_REGS_GICD_AFFINITY2_893_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_893_LEN    8
#define GICD_REGS_GICD_AFFINITY1_893_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_893_LEN    8
#define GICD_REGS_GICD_AFFINITY0_893_OFFSET 0

#define GICD_REGS_GICD_IRM_894_LEN          1
#define GICD_REGS_GICD_IRM_894_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_894_LEN    8
#define GICD_REGS_GICD_AFFINITY2_894_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_894_LEN    8
#define GICD_REGS_GICD_AFFINITY1_894_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_894_LEN    8
#define GICD_REGS_GICD_AFFINITY0_894_OFFSET 0

#define GICD_REGS_GICD_IRM_895_LEN          1
#define GICD_REGS_GICD_IRM_895_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_895_LEN    8
#define GICD_REGS_GICD_AFFINITY2_895_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_895_LEN    8
#define GICD_REGS_GICD_AFFINITY1_895_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_895_LEN    8
#define GICD_REGS_GICD_AFFINITY0_895_OFFSET 0

#define GICD_REGS_GICD_IRM_896_LEN          1
#define GICD_REGS_GICD_IRM_896_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_896_LEN    8
#define GICD_REGS_GICD_AFFINITY2_896_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_896_LEN    8
#define GICD_REGS_GICD_AFFINITY1_896_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_896_LEN    8
#define GICD_REGS_GICD_AFFINITY0_896_OFFSET 0

#define GICD_REGS_GICD_IRM_897_LEN          1
#define GICD_REGS_GICD_IRM_897_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_897_LEN    8
#define GICD_REGS_GICD_AFFINITY2_897_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_897_LEN    8
#define GICD_REGS_GICD_AFFINITY1_897_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_897_LEN    8
#define GICD_REGS_GICD_AFFINITY0_897_OFFSET 0

#define GICD_REGS_GICD_IRM_898_LEN          1
#define GICD_REGS_GICD_IRM_898_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_898_LEN    8
#define GICD_REGS_GICD_AFFINITY2_898_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_898_LEN    8
#define GICD_REGS_GICD_AFFINITY1_898_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_898_LEN    8
#define GICD_REGS_GICD_AFFINITY0_898_OFFSET 0

#define GICD_REGS_GICD_IRM_899_LEN          1
#define GICD_REGS_GICD_IRM_899_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_899_LEN    8
#define GICD_REGS_GICD_AFFINITY2_899_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_899_LEN    8
#define GICD_REGS_GICD_AFFINITY1_899_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_899_LEN    8
#define GICD_REGS_GICD_AFFINITY0_899_OFFSET 0

#define GICD_REGS_GICD_IRM_900_LEN          1
#define GICD_REGS_GICD_IRM_900_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_900_LEN    8
#define GICD_REGS_GICD_AFFINITY2_900_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_900_LEN    8
#define GICD_REGS_GICD_AFFINITY1_900_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_900_LEN    8
#define GICD_REGS_GICD_AFFINITY0_900_OFFSET 0

#define GICD_REGS_GICD_IRM_901_LEN          1
#define GICD_REGS_GICD_IRM_901_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_901_LEN    8
#define GICD_REGS_GICD_AFFINITY2_901_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_901_LEN    8
#define GICD_REGS_GICD_AFFINITY1_901_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_901_LEN    8
#define GICD_REGS_GICD_AFFINITY0_901_OFFSET 0

#define GICD_REGS_GICD_IRM_902_LEN          1
#define GICD_REGS_GICD_IRM_902_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_902_LEN    8
#define GICD_REGS_GICD_AFFINITY2_902_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_902_LEN    8
#define GICD_REGS_GICD_AFFINITY1_902_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_902_LEN    8
#define GICD_REGS_GICD_AFFINITY0_902_OFFSET 0

#define GICD_REGS_GICD_IRM_903_LEN          1
#define GICD_REGS_GICD_IRM_903_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_903_LEN    8
#define GICD_REGS_GICD_AFFINITY2_903_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_903_LEN    8
#define GICD_REGS_GICD_AFFINITY1_903_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_903_LEN    8
#define GICD_REGS_GICD_AFFINITY0_903_OFFSET 0

#define GICD_REGS_GICD_IRM_904_LEN          1
#define GICD_REGS_GICD_IRM_904_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_904_LEN    8
#define GICD_REGS_GICD_AFFINITY2_904_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_904_LEN    8
#define GICD_REGS_GICD_AFFINITY1_904_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_904_LEN    8
#define GICD_REGS_GICD_AFFINITY0_904_OFFSET 0

#define GICD_REGS_GICD_IRM_905_LEN          1
#define GICD_REGS_GICD_IRM_905_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_905_LEN    8
#define GICD_REGS_GICD_AFFINITY2_905_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_905_LEN    8
#define GICD_REGS_GICD_AFFINITY1_905_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_905_LEN    8
#define GICD_REGS_GICD_AFFINITY0_905_OFFSET 0

#define GICD_REGS_GICD_IRM_906_LEN          1
#define GICD_REGS_GICD_IRM_906_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_906_LEN    8
#define GICD_REGS_GICD_AFFINITY2_906_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_906_LEN    8
#define GICD_REGS_GICD_AFFINITY1_906_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_906_LEN    8
#define GICD_REGS_GICD_AFFINITY0_906_OFFSET 0

#define GICD_REGS_GICD_IRM_907_LEN          1
#define GICD_REGS_GICD_IRM_907_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_907_LEN    8
#define GICD_REGS_GICD_AFFINITY2_907_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_907_LEN    8
#define GICD_REGS_GICD_AFFINITY1_907_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_907_LEN    8
#define GICD_REGS_GICD_AFFINITY0_907_OFFSET 0

#define GICD_REGS_GICD_IRM_908_LEN          1
#define GICD_REGS_GICD_IRM_908_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_908_LEN    8
#define GICD_REGS_GICD_AFFINITY2_908_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_908_LEN    8
#define GICD_REGS_GICD_AFFINITY1_908_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_908_LEN    8
#define GICD_REGS_GICD_AFFINITY0_908_OFFSET 0

#define GICD_REGS_GICD_IRM_909_LEN          1
#define GICD_REGS_GICD_IRM_909_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_909_LEN    8
#define GICD_REGS_GICD_AFFINITY2_909_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_909_LEN    8
#define GICD_REGS_GICD_AFFINITY1_909_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_909_LEN    8
#define GICD_REGS_GICD_AFFINITY0_909_OFFSET 0

#define GICD_REGS_GICD_IRM_910_LEN          1
#define GICD_REGS_GICD_IRM_910_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_910_LEN    8
#define GICD_REGS_GICD_AFFINITY2_910_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_910_LEN    8
#define GICD_REGS_GICD_AFFINITY1_910_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_910_LEN    8
#define GICD_REGS_GICD_AFFINITY0_910_OFFSET 0

#define GICD_REGS_GICD_IRM_911_LEN          1
#define GICD_REGS_GICD_IRM_911_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_911_LEN    8
#define GICD_REGS_GICD_AFFINITY2_911_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_911_LEN    8
#define GICD_REGS_GICD_AFFINITY1_911_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_911_LEN    8
#define GICD_REGS_GICD_AFFINITY0_911_OFFSET 0

#define GICD_REGS_GICD_IRM_912_LEN          1
#define GICD_REGS_GICD_IRM_912_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_912_LEN    8
#define GICD_REGS_GICD_AFFINITY2_912_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_912_LEN    8
#define GICD_REGS_GICD_AFFINITY1_912_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_912_LEN    8
#define GICD_REGS_GICD_AFFINITY0_912_OFFSET 0

#define GICD_REGS_GICD_IRM_913_LEN          1
#define GICD_REGS_GICD_IRM_913_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_913_LEN    8
#define GICD_REGS_GICD_AFFINITY2_913_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_913_LEN    8
#define GICD_REGS_GICD_AFFINITY1_913_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_913_LEN    8
#define GICD_REGS_GICD_AFFINITY0_913_OFFSET 0

#define GICD_REGS_GICD_IRM_914_LEN          1
#define GICD_REGS_GICD_IRM_914_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_914_LEN    8
#define GICD_REGS_GICD_AFFINITY2_914_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_914_LEN    8
#define GICD_REGS_GICD_AFFINITY1_914_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_914_LEN    8
#define GICD_REGS_GICD_AFFINITY0_914_OFFSET 0

#define GICD_REGS_GICD_IRM_915_LEN          1
#define GICD_REGS_GICD_IRM_915_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_915_LEN    8
#define GICD_REGS_GICD_AFFINITY2_915_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_915_LEN    8
#define GICD_REGS_GICD_AFFINITY1_915_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_915_LEN    8
#define GICD_REGS_GICD_AFFINITY0_915_OFFSET 0

#define GICD_REGS_GICD_IRM_916_LEN          1
#define GICD_REGS_GICD_IRM_916_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_916_LEN    8
#define GICD_REGS_GICD_AFFINITY2_916_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_916_LEN    8
#define GICD_REGS_GICD_AFFINITY1_916_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_916_LEN    8
#define GICD_REGS_GICD_AFFINITY0_916_OFFSET 0

#define GICD_REGS_GICD_IRM_917_LEN          1
#define GICD_REGS_GICD_IRM_917_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_917_LEN    8
#define GICD_REGS_GICD_AFFINITY2_917_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_917_LEN    8
#define GICD_REGS_GICD_AFFINITY1_917_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_917_LEN    8
#define GICD_REGS_GICD_AFFINITY0_917_OFFSET 0

#define GICD_REGS_GICD_IRM_918_LEN          1
#define GICD_REGS_GICD_IRM_918_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_918_LEN    8
#define GICD_REGS_GICD_AFFINITY2_918_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_918_LEN    8
#define GICD_REGS_GICD_AFFINITY1_918_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_918_LEN    8
#define GICD_REGS_GICD_AFFINITY0_918_OFFSET 0

#define GICD_REGS_GICD_IRM_919_LEN          1
#define GICD_REGS_GICD_IRM_919_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_919_LEN    8
#define GICD_REGS_GICD_AFFINITY2_919_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_919_LEN    8
#define GICD_REGS_GICD_AFFINITY1_919_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_919_LEN    8
#define GICD_REGS_GICD_AFFINITY0_919_OFFSET 0

#define GICD_REGS_GICD_IRM_920_LEN          1
#define GICD_REGS_GICD_IRM_920_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_920_LEN    8
#define GICD_REGS_GICD_AFFINITY2_920_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_920_LEN    8
#define GICD_REGS_GICD_AFFINITY1_920_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_920_LEN    8
#define GICD_REGS_GICD_AFFINITY0_920_OFFSET 0

#define GICD_REGS_GICD_IRM_921_LEN          1
#define GICD_REGS_GICD_IRM_921_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_921_LEN    8
#define GICD_REGS_GICD_AFFINITY2_921_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_921_LEN    8
#define GICD_REGS_GICD_AFFINITY1_921_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_921_LEN    8
#define GICD_REGS_GICD_AFFINITY0_921_OFFSET 0

#define GICD_REGS_GICD_IRM_922_LEN          1
#define GICD_REGS_GICD_IRM_922_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_922_LEN    8
#define GICD_REGS_GICD_AFFINITY2_922_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_922_LEN    8
#define GICD_REGS_GICD_AFFINITY1_922_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_922_LEN    8
#define GICD_REGS_GICD_AFFINITY0_922_OFFSET 0

#define GICD_REGS_GICD_IRM_923_LEN          1
#define GICD_REGS_GICD_IRM_923_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_923_LEN    8
#define GICD_REGS_GICD_AFFINITY2_923_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_923_LEN    8
#define GICD_REGS_GICD_AFFINITY1_923_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_923_LEN    8
#define GICD_REGS_GICD_AFFINITY0_923_OFFSET 0

#define GICD_REGS_GICD_IRM_924_LEN          1
#define GICD_REGS_GICD_IRM_924_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_924_LEN    8
#define GICD_REGS_GICD_AFFINITY2_924_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_924_LEN    8
#define GICD_REGS_GICD_AFFINITY1_924_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_924_LEN    8
#define GICD_REGS_GICD_AFFINITY0_924_OFFSET 0

#define GICD_REGS_GICD_IRM_925_LEN          1
#define GICD_REGS_GICD_IRM_925_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_925_LEN    8
#define GICD_REGS_GICD_AFFINITY2_925_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_925_LEN    8
#define GICD_REGS_GICD_AFFINITY1_925_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_925_LEN    8
#define GICD_REGS_GICD_AFFINITY0_925_OFFSET 0

#define GICD_REGS_GICD_IRM_926_LEN          1
#define GICD_REGS_GICD_IRM_926_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_926_LEN    8
#define GICD_REGS_GICD_AFFINITY2_926_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_926_LEN    8
#define GICD_REGS_GICD_AFFINITY1_926_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_926_LEN    8
#define GICD_REGS_GICD_AFFINITY0_926_OFFSET 0

#define GICD_REGS_GICD_IRM_927_LEN          1
#define GICD_REGS_GICD_IRM_927_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_927_LEN    8
#define GICD_REGS_GICD_AFFINITY2_927_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_927_LEN    8
#define GICD_REGS_GICD_AFFINITY1_927_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_927_LEN    8
#define GICD_REGS_GICD_AFFINITY0_927_OFFSET 0

#define GICD_REGS_GICD_IRM_928_LEN          1
#define GICD_REGS_GICD_IRM_928_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_928_LEN    8
#define GICD_REGS_GICD_AFFINITY2_928_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_928_LEN    8
#define GICD_REGS_GICD_AFFINITY1_928_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_928_LEN    8
#define GICD_REGS_GICD_AFFINITY0_928_OFFSET 0

#define GICD_REGS_GICD_IRM_929_LEN          1
#define GICD_REGS_GICD_IRM_929_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_929_LEN    8
#define GICD_REGS_GICD_AFFINITY2_929_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_929_LEN    8
#define GICD_REGS_GICD_AFFINITY1_929_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_929_LEN    8
#define GICD_REGS_GICD_AFFINITY0_929_OFFSET 0

#define GICD_REGS_GICD_IRM_930_LEN          1
#define GICD_REGS_GICD_IRM_930_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_930_LEN    8
#define GICD_REGS_GICD_AFFINITY2_930_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_930_LEN    8
#define GICD_REGS_GICD_AFFINITY1_930_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_930_LEN    8
#define GICD_REGS_GICD_AFFINITY0_930_OFFSET 0

#define GICD_REGS_GICD_IRM_931_LEN          1
#define GICD_REGS_GICD_IRM_931_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_931_LEN    8
#define GICD_REGS_GICD_AFFINITY2_931_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_931_LEN    8
#define GICD_REGS_GICD_AFFINITY1_931_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_931_LEN    8
#define GICD_REGS_GICD_AFFINITY0_931_OFFSET 0

#define GICD_REGS_GICD_IRM_932_LEN          1
#define GICD_REGS_GICD_IRM_932_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_932_LEN    8
#define GICD_REGS_GICD_AFFINITY2_932_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_932_LEN    8
#define GICD_REGS_GICD_AFFINITY1_932_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_932_LEN    8
#define GICD_REGS_GICD_AFFINITY0_932_OFFSET 0

#define GICD_REGS_GICD_IRM_933_LEN          1
#define GICD_REGS_GICD_IRM_933_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_933_LEN    8
#define GICD_REGS_GICD_AFFINITY2_933_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_933_LEN    8
#define GICD_REGS_GICD_AFFINITY1_933_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_933_LEN    8
#define GICD_REGS_GICD_AFFINITY0_933_OFFSET 0

#define GICD_REGS_GICD_IRM_934_LEN          1
#define GICD_REGS_GICD_IRM_934_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_934_LEN    8
#define GICD_REGS_GICD_AFFINITY2_934_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_934_LEN    8
#define GICD_REGS_GICD_AFFINITY1_934_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_934_LEN    8
#define GICD_REGS_GICD_AFFINITY0_934_OFFSET 0

#define GICD_REGS_GICD_IRM_935_LEN          1
#define GICD_REGS_GICD_IRM_935_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_935_LEN    8
#define GICD_REGS_GICD_AFFINITY2_935_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_935_LEN    8
#define GICD_REGS_GICD_AFFINITY1_935_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_935_LEN    8
#define GICD_REGS_GICD_AFFINITY0_935_OFFSET 0

#define GICD_REGS_GICD_IRM_936_LEN          1
#define GICD_REGS_GICD_IRM_936_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_936_LEN    8
#define GICD_REGS_GICD_AFFINITY2_936_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_936_LEN    8
#define GICD_REGS_GICD_AFFINITY1_936_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_936_LEN    8
#define GICD_REGS_GICD_AFFINITY0_936_OFFSET 0

#define GICD_REGS_GICD_IRM_937_LEN          1
#define GICD_REGS_GICD_IRM_937_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_937_LEN    8
#define GICD_REGS_GICD_AFFINITY2_937_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_937_LEN    8
#define GICD_REGS_GICD_AFFINITY1_937_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_937_LEN    8
#define GICD_REGS_GICD_AFFINITY0_937_OFFSET 0

#define GICD_REGS_GICD_IRM_938_LEN          1
#define GICD_REGS_GICD_IRM_938_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_938_LEN    8
#define GICD_REGS_GICD_AFFINITY2_938_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_938_LEN    8
#define GICD_REGS_GICD_AFFINITY1_938_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_938_LEN    8
#define GICD_REGS_GICD_AFFINITY0_938_OFFSET 0

#define GICD_REGS_GICD_IRM_939_LEN          1
#define GICD_REGS_GICD_IRM_939_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_939_LEN    8
#define GICD_REGS_GICD_AFFINITY2_939_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_939_LEN    8
#define GICD_REGS_GICD_AFFINITY1_939_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_939_LEN    8
#define GICD_REGS_GICD_AFFINITY0_939_OFFSET 0

#define GICD_REGS_GICD_IRM_940_LEN          1
#define GICD_REGS_GICD_IRM_940_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_940_LEN    8
#define GICD_REGS_GICD_AFFINITY2_940_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_940_LEN    8
#define GICD_REGS_GICD_AFFINITY1_940_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_940_LEN    8
#define GICD_REGS_GICD_AFFINITY0_940_OFFSET 0

#define GICD_REGS_GICD_IRM_941_LEN          1
#define GICD_REGS_GICD_IRM_941_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_941_LEN    8
#define GICD_REGS_GICD_AFFINITY2_941_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_941_LEN    8
#define GICD_REGS_GICD_AFFINITY1_941_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_941_LEN    8
#define GICD_REGS_GICD_AFFINITY0_941_OFFSET 0

#define GICD_REGS_GICD_IRM_942_LEN          1
#define GICD_REGS_GICD_IRM_942_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_942_LEN    8
#define GICD_REGS_GICD_AFFINITY2_942_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_942_LEN    8
#define GICD_REGS_GICD_AFFINITY1_942_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_942_LEN    8
#define GICD_REGS_GICD_AFFINITY0_942_OFFSET 0

#define GICD_REGS_GICD_IRM_943_LEN          1
#define GICD_REGS_GICD_IRM_943_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_943_LEN    8
#define GICD_REGS_GICD_AFFINITY2_943_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_943_LEN    8
#define GICD_REGS_GICD_AFFINITY1_943_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_943_LEN    8
#define GICD_REGS_GICD_AFFINITY0_943_OFFSET 0

#define GICD_REGS_GICD_IRM_944_LEN          1
#define GICD_REGS_GICD_IRM_944_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_944_LEN    8
#define GICD_REGS_GICD_AFFINITY2_944_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_944_LEN    8
#define GICD_REGS_GICD_AFFINITY1_944_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_944_LEN    8
#define GICD_REGS_GICD_AFFINITY0_944_OFFSET 0

#define GICD_REGS_GICD_IRM_945_LEN          1
#define GICD_REGS_GICD_IRM_945_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_945_LEN    8
#define GICD_REGS_GICD_AFFINITY2_945_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_945_LEN    8
#define GICD_REGS_GICD_AFFINITY1_945_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_945_LEN    8
#define GICD_REGS_GICD_AFFINITY0_945_OFFSET 0

#define GICD_REGS_GICD_IRM_946_LEN          1
#define GICD_REGS_GICD_IRM_946_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_946_LEN    8
#define GICD_REGS_GICD_AFFINITY2_946_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_946_LEN    8
#define GICD_REGS_GICD_AFFINITY1_946_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_946_LEN    8
#define GICD_REGS_GICD_AFFINITY0_946_OFFSET 0

#define GICD_REGS_GICD_IRM_947_LEN          1
#define GICD_REGS_GICD_IRM_947_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_947_LEN    8
#define GICD_REGS_GICD_AFFINITY2_947_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_947_LEN    8
#define GICD_REGS_GICD_AFFINITY1_947_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_947_LEN    8
#define GICD_REGS_GICD_AFFINITY0_947_OFFSET 0

#define GICD_REGS_GICD_IRM_948_LEN          1
#define GICD_REGS_GICD_IRM_948_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_948_LEN    8
#define GICD_REGS_GICD_AFFINITY2_948_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_948_LEN    8
#define GICD_REGS_GICD_AFFINITY1_948_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_948_LEN    8
#define GICD_REGS_GICD_AFFINITY0_948_OFFSET 0

#define GICD_REGS_GICD_IRM_949_LEN          1
#define GICD_REGS_GICD_IRM_949_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_949_LEN    8
#define GICD_REGS_GICD_AFFINITY2_949_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_949_LEN    8
#define GICD_REGS_GICD_AFFINITY1_949_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_949_LEN    8
#define GICD_REGS_GICD_AFFINITY0_949_OFFSET 0

#define GICD_REGS_GICD_IRM_950_LEN          1
#define GICD_REGS_GICD_IRM_950_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_950_LEN    8
#define GICD_REGS_GICD_AFFINITY2_950_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_950_LEN    8
#define GICD_REGS_GICD_AFFINITY1_950_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_950_LEN    8
#define GICD_REGS_GICD_AFFINITY0_950_OFFSET 0

#define GICD_REGS_GICD_IRM_951_LEN          1
#define GICD_REGS_GICD_IRM_951_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_951_LEN    8
#define GICD_REGS_GICD_AFFINITY2_951_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_951_LEN    8
#define GICD_REGS_GICD_AFFINITY1_951_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_951_LEN    8
#define GICD_REGS_GICD_AFFINITY0_951_OFFSET 0

#define GICD_REGS_GICD_IRM_952_LEN          1
#define GICD_REGS_GICD_IRM_952_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_952_LEN    8
#define GICD_REGS_GICD_AFFINITY2_952_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_952_LEN    8
#define GICD_REGS_GICD_AFFINITY1_952_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_952_LEN    8
#define GICD_REGS_GICD_AFFINITY0_952_OFFSET 0

#define GICD_REGS_GICD_IRM_953_LEN          1
#define GICD_REGS_GICD_IRM_953_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_953_LEN    8
#define GICD_REGS_GICD_AFFINITY2_953_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_953_LEN    8
#define GICD_REGS_GICD_AFFINITY1_953_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_953_LEN    8
#define GICD_REGS_GICD_AFFINITY0_953_OFFSET 0

#define GICD_REGS_GICD_IRM_954_LEN          1
#define GICD_REGS_GICD_IRM_954_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_954_LEN    8
#define GICD_REGS_GICD_AFFINITY2_954_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_954_LEN    8
#define GICD_REGS_GICD_AFFINITY1_954_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_954_LEN    8
#define GICD_REGS_GICD_AFFINITY0_954_OFFSET 0

#define GICD_REGS_GICD_IRM_955_LEN          1
#define GICD_REGS_GICD_IRM_955_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_955_LEN    8
#define GICD_REGS_GICD_AFFINITY2_955_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_955_LEN    8
#define GICD_REGS_GICD_AFFINITY1_955_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_955_LEN    8
#define GICD_REGS_GICD_AFFINITY0_955_OFFSET 0

#define GICD_REGS_GICD_IRM_956_LEN          1
#define GICD_REGS_GICD_IRM_956_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_956_LEN    8
#define GICD_REGS_GICD_AFFINITY2_956_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_956_LEN    8
#define GICD_REGS_GICD_AFFINITY1_956_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_956_LEN    8
#define GICD_REGS_GICD_AFFINITY0_956_OFFSET 0

#define GICD_REGS_GICD_IRM_957_LEN          1
#define GICD_REGS_GICD_IRM_957_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_957_LEN    8
#define GICD_REGS_GICD_AFFINITY2_957_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_957_LEN    8
#define GICD_REGS_GICD_AFFINITY1_957_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_957_LEN    8
#define GICD_REGS_GICD_AFFINITY0_957_OFFSET 0

#define GICD_REGS_GICD_IRM_958_LEN          1
#define GICD_REGS_GICD_IRM_958_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_958_LEN    8
#define GICD_REGS_GICD_AFFINITY2_958_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_958_LEN    8
#define GICD_REGS_GICD_AFFINITY1_958_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_958_LEN    8
#define GICD_REGS_GICD_AFFINITY0_958_OFFSET 0

#define GICD_REGS_GICD_IRM_959_LEN          1
#define GICD_REGS_GICD_IRM_959_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_959_LEN    8
#define GICD_REGS_GICD_AFFINITY2_959_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_959_LEN    8
#define GICD_REGS_GICD_AFFINITY1_959_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_959_LEN    8
#define GICD_REGS_GICD_AFFINITY0_959_OFFSET 0

#define GICD_REGS_GICD_IRM_960_LEN          1
#define GICD_REGS_GICD_IRM_960_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_960_LEN    8
#define GICD_REGS_GICD_AFFINITY2_960_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_960_LEN    8
#define GICD_REGS_GICD_AFFINITY1_960_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_960_LEN    8
#define GICD_REGS_GICD_AFFINITY0_960_OFFSET 0

#define GICD_REGS_GICD_IRM_961_LEN          1
#define GICD_REGS_GICD_IRM_961_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_961_LEN    8
#define GICD_REGS_GICD_AFFINITY2_961_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_961_LEN    8
#define GICD_REGS_GICD_AFFINITY1_961_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_961_LEN    8
#define GICD_REGS_GICD_AFFINITY0_961_OFFSET 0

#define GICD_REGS_GICD_IRM_962_LEN          1
#define GICD_REGS_GICD_IRM_962_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_962_LEN    8
#define GICD_REGS_GICD_AFFINITY2_962_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_962_LEN    8
#define GICD_REGS_GICD_AFFINITY1_962_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_962_LEN    8
#define GICD_REGS_GICD_AFFINITY0_962_OFFSET 0

#define GICD_REGS_GICD_IRM_963_LEN          1
#define GICD_REGS_GICD_IRM_963_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_963_LEN    8
#define GICD_REGS_GICD_AFFINITY2_963_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_963_LEN    8
#define GICD_REGS_GICD_AFFINITY1_963_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_963_LEN    8
#define GICD_REGS_GICD_AFFINITY0_963_OFFSET 0

#define GICD_REGS_GICD_IRM_964_LEN          1
#define GICD_REGS_GICD_IRM_964_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_964_LEN    8
#define GICD_REGS_GICD_AFFINITY2_964_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_964_LEN    8
#define GICD_REGS_GICD_AFFINITY1_964_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_964_LEN    8
#define GICD_REGS_GICD_AFFINITY0_964_OFFSET 0

#define GICD_REGS_GICD_IRM_965_LEN          1
#define GICD_REGS_GICD_IRM_965_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_965_LEN    8
#define GICD_REGS_GICD_AFFINITY2_965_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_965_LEN    8
#define GICD_REGS_GICD_AFFINITY1_965_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_965_LEN    8
#define GICD_REGS_GICD_AFFINITY0_965_OFFSET 0

#define GICD_REGS_GICD_IRM_966_LEN          1
#define GICD_REGS_GICD_IRM_966_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_966_LEN    8
#define GICD_REGS_GICD_AFFINITY2_966_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_966_LEN    8
#define GICD_REGS_GICD_AFFINITY1_966_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_966_LEN    8
#define GICD_REGS_GICD_AFFINITY0_966_OFFSET 0

#define GICD_REGS_GICD_IRM_967_LEN          1
#define GICD_REGS_GICD_IRM_967_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_967_LEN    8
#define GICD_REGS_GICD_AFFINITY2_967_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_967_LEN    8
#define GICD_REGS_GICD_AFFINITY1_967_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_967_LEN    8
#define GICD_REGS_GICD_AFFINITY0_967_OFFSET 0

#define GICD_REGS_GICD_IRM_968_LEN          1
#define GICD_REGS_GICD_IRM_968_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_968_LEN    8
#define GICD_REGS_GICD_AFFINITY2_968_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_968_LEN    8
#define GICD_REGS_GICD_AFFINITY1_968_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_968_LEN    8
#define GICD_REGS_GICD_AFFINITY0_968_OFFSET 0

#define GICD_REGS_GICD_IRM_969_LEN          1
#define GICD_REGS_GICD_IRM_969_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_969_LEN    8
#define GICD_REGS_GICD_AFFINITY2_969_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_969_LEN    8
#define GICD_REGS_GICD_AFFINITY1_969_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_969_LEN    8
#define GICD_REGS_GICD_AFFINITY0_969_OFFSET 0

#define GICD_REGS_GICD_IRM_970_LEN          1
#define GICD_REGS_GICD_IRM_970_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_970_LEN    8
#define GICD_REGS_GICD_AFFINITY2_970_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_970_LEN    8
#define GICD_REGS_GICD_AFFINITY1_970_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_970_LEN    8
#define GICD_REGS_GICD_AFFINITY0_970_OFFSET 0

#define GICD_REGS_GICD_IRM_971_LEN          1
#define GICD_REGS_GICD_IRM_971_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_971_LEN    8
#define GICD_REGS_GICD_AFFINITY2_971_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_971_LEN    8
#define GICD_REGS_GICD_AFFINITY1_971_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_971_LEN    8
#define GICD_REGS_GICD_AFFINITY0_971_OFFSET 0

#define GICD_REGS_GICD_IRM_972_LEN          1
#define GICD_REGS_GICD_IRM_972_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_972_LEN    8
#define GICD_REGS_GICD_AFFINITY2_972_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_972_LEN    8
#define GICD_REGS_GICD_AFFINITY1_972_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_972_LEN    8
#define GICD_REGS_GICD_AFFINITY0_972_OFFSET 0

#define GICD_REGS_GICD_IRM_973_LEN          1
#define GICD_REGS_GICD_IRM_973_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_973_LEN    8
#define GICD_REGS_GICD_AFFINITY2_973_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_973_LEN    8
#define GICD_REGS_GICD_AFFINITY1_973_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_973_LEN    8
#define GICD_REGS_GICD_AFFINITY0_973_OFFSET 0

#define GICD_REGS_GICD_IRM_974_LEN          1
#define GICD_REGS_GICD_IRM_974_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_974_LEN    8
#define GICD_REGS_GICD_AFFINITY2_974_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_974_LEN    8
#define GICD_REGS_GICD_AFFINITY1_974_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_974_LEN    8
#define GICD_REGS_GICD_AFFINITY0_974_OFFSET 0

#define GICD_REGS_GICD_IRM_975_LEN          1
#define GICD_REGS_GICD_IRM_975_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_975_LEN    8
#define GICD_REGS_GICD_AFFINITY2_975_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_975_LEN    8
#define GICD_REGS_GICD_AFFINITY1_975_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_975_LEN    8
#define GICD_REGS_GICD_AFFINITY0_975_OFFSET 0

#define GICD_REGS_GICD_IRM_976_LEN          1
#define GICD_REGS_GICD_IRM_976_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_976_LEN    8
#define GICD_REGS_GICD_AFFINITY2_976_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_976_LEN    8
#define GICD_REGS_GICD_AFFINITY1_976_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_976_LEN    8
#define GICD_REGS_GICD_AFFINITY0_976_OFFSET 0

#define GICD_REGS_GICD_IRM_977_LEN          1
#define GICD_REGS_GICD_IRM_977_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_977_LEN    8
#define GICD_REGS_GICD_AFFINITY2_977_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_977_LEN    8
#define GICD_REGS_GICD_AFFINITY1_977_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_977_LEN    8
#define GICD_REGS_GICD_AFFINITY0_977_OFFSET 0

#define GICD_REGS_GICD_IRM_978_LEN          1
#define GICD_REGS_GICD_IRM_978_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_978_LEN    8
#define GICD_REGS_GICD_AFFINITY2_978_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_978_LEN    8
#define GICD_REGS_GICD_AFFINITY1_978_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_978_LEN    8
#define GICD_REGS_GICD_AFFINITY0_978_OFFSET 0

#define GICD_REGS_GICD_IRM_979_LEN          1
#define GICD_REGS_GICD_IRM_979_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_979_LEN    8
#define GICD_REGS_GICD_AFFINITY2_979_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_979_LEN    8
#define GICD_REGS_GICD_AFFINITY1_979_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_979_LEN    8
#define GICD_REGS_GICD_AFFINITY0_979_OFFSET 0

#define GICD_REGS_GICD_IRM_980_LEN          1
#define GICD_REGS_GICD_IRM_980_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_980_LEN    8
#define GICD_REGS_GICD_AFFINITY2_980_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_980_LEN    8
#define GICD_REGS_GICD_AFFINITY1_980_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_980_LEN    8
#define GICD_REGS_GICD_AFFINITY0_980_OFFSET 0

#define GICD_REGS_GICD_IRM_981_LEN          1
#define GICD_REGS_GICD_IRM_981_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_981_LEN    8
#define GICD_REGS_GICD_AFFINITY2_981_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_981_LEN    8
#define GICD_REGS_GICD_AFFINITY1_981_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_981_LEN    8
#define GICD_REGS_GICD_AFFINITY0_981_OFFSET 0

#define GICD_REGS_GICD_IRM_982_LEN          1
#define GICD_REGS_GICD_IRM_982_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_982_LEN    8
#define GICD_REGS_GICD_AFFINITY2_982_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_982_LEN    8
#define GICD_REGS_GICD_AFFINITY1_982_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_982_LEN    8
#define GICD_REGS_GICD_AFFINITY0_982_OFFSET 0

#define GICD_REGS_GICD_IRM_983_LEN          1
#define GICD_REGS_GICD_IRM_983_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_983_LEN    8
#define GICD_REGS_GICD_AFFINITY2_983_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_983_LEN    8
#define GICD_REGS_GICD_AFFINITY1_983_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_983_LEN    8
#define GICD_REGS_GICD_AFFINITY0_983_OFFSET 0

#define GICD_REGS_GICD_IRM_984_LEN          1
#define GICD_REGS_GICD_IRM_984_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_984_LEN    8
#define GICD_REGS_GICD_AFFINITY2_984_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_984_LEN    8
#define GICD_REGS_GICD_AFFINITY1_984_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_984_LEN    8
#define GICD_REGS_GICD_AFFINITY0_984_OFFSET 0

#define GICD_REGS_GICD_IRM_985_LEN          1
#define GICD_REGS_GICD_IRM_985_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_985_LEN    8
#define GICD_REGS_GICD_AFFINITY2_985_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_985_LEN    8
#define GICD_REGS_GICD_AFFINITY1_985_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_985_LEN    8
#define GICD_REGS_GICD_AFFINITY0_985_OFFSET 0

#define GICD_REGS_GICD_IRM_986_LEN          1
#define GICD_REGS_GICD_IRM_986_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_986_LEN    8
#define GICD_REGS_GICD_AFFINITY2_986_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_986_LEN    8
#define GICD_REGS_GICD_AFFINITY1_986_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_986_LEN    8
#define GICD_REGS_GICD_AFFINITY0_986_OFFSET 0

#define GICD_REGS_GICD_IRM_987_LEN          1
#define GICD_REGS_GICD_IRM_987_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_987_LEN    8
#define GICD_REGS_GICD_AFFINITY2_987_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_987_LEN    8
#define GICD_REGS_GICD_AFFINITY1_987_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_987_LEN    8
#define GICD_REGS_GICD_AFFINITY0_987_OFFSET 0

#define GICD_REGS_GICD_IRM_988_LEN          1
#define GICD_REGS_GICD_IRM_988_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_988_LEN    8
#define GICD_REGS_GICD_AFFINITY2_988_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_988_LEN    8
#define GICD_REGS_GICD_AFFINITY1_988_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_988_LEN    8
#define GICD_REGS_GICD_AFFINITY0_988_OFFSET 0

#define GICD_REGS_GICD_IRM_989_LEN          1
#define GICD_REGS_GICD_IRM_989_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_989_LEN    8
#define GICD_REGS_GICD_AFFINITY2_989_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_989_LEN    8
#define GICD_REGS_GICD_AFFINITY1_989_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_989_LEN    8
#define GICD_REGS_GICD_AFFINITY0_989_OFFSET 0

#define GICD_REGS_GICD_IRM_990_LEN          1
#define GICD_REGS_GICD_IRM_990_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_990_LEN    8
#define GICD_REGS_GICD_AFFINITY2_990_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_990_LEN    8
#define GICD_REGS_GICD_AFFINITY1_990_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_990_LEN    8
#define GICD_REGS_GICD_AFFINITY0_990_OFFSET 0

#define GICD_REGS_GICD_IRM_991_LEN          1
#define GICD_REGS_GICD_IRM_991_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_991_LEN    8
#define GICD_REGS_GICD_AFFINITY2_991_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_991_LEN    8
#define GICD_REGS_GICD_AFFINITY1_991_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_991_LEN    8
#define GICD_REGS_GICD_AFFINITY0_991_OFFSET 0

#define GICD_REGS_GICD_IRM_992_LEN          1
#define GICD_REGS_GICD_IRM_992_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_992_LEN    8
#define GICD_REGS_GICD_AFFINITY2_992_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_992_LEN    8
#define GICD_REGS_GICD_AFFINITY1_992_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_992_LEN    8
#define GICD_REGS_GICD_AFFINITY0_992_OFFSET 0

#define GICD_REGS_GICD_IRM_993_LEN          1
#define GICD_REGS_GICD_IRM_993_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_993_LEN    8
#define GICD_REGS_GICD_AFFINITY2_993_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_993_LEN    8
#define GICD_REGS_GICD_AFFINITY1_993_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_993_LEN    8
#define GICD_REGS_GICD_AFFINITY0_993_OFFSET 0

#define GICD_REGS_GICD_IRM_994_LEN          1
#define GICD_REGS_GICD_IRM_994_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_994_LEN    8
#define GICD_REGS_GICD_AFFINITY2_994_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_994_LEN    8
#define GICD_REGS_GICD_AFFINITY1_994_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_994_LEN    8
#define GICD_REGS_GICD_AFFINITY0_994_OFFSET 0

#define GICD_REGS_GICD_IRM_995_LEN          1
#define GICD_REGS_GICD_IRM_995_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_995_LEN    8
#define GICD_REGS_GICD_AFFINITY2_995_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_995_LEN    8
#define GICD_REGS_GICD_AFFINITY1_995_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_995_LEN    8
#define GICD_REGS_GICD_AFFINITY0_995_OFFSET 0

#define GICD_REGS_GICD_IRM_996_LEN          1
#define GICD_REGS_GICD_IRM_996_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_996_LEN    8
#define GICD_REGS_GICD_AFFINITY2_996_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_996_LEN    8
#define GICD_REGS_GICD_AFFINITY1_996_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_996_LEN    8
#define GICD_REGS_GICD_AFFINITY0_996_OFFSET 0

#define GICD_REGS_GICD_IRM_997_LEN          1
#define GICD_REGS_GICD_IRM_997_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_997_LEN    8
#define GICD_REGS_GICD_AFFINITY2_997_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_997_LEN    8
#define GICD_REGS_GICD_AFFINITY1_997_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_997_LEN    8
#define GICD_REGS_GICD_AFFINITY0_997_OFFSET 0

#define GICD_REGS_GICD_IRM_998_LEN          1
#define GICD_REGS_GICD_IRM_998_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_998_LEN    8
#define GICD_REGS_GICD_AFFINITY2_998_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_998_LEN    8
#define GICD_REGS_GICD_AFFINITY1_998_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_998_LEN    8
#define GICD_REGS_GICD_AFFINITY0_998_OFFSET 0

#define GICD_REGS_GICD_IRM_999_LEN          1
#define GICD_REGS_GICD_IRM_999_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_999_LEN    8
#define GICD_REGS_GICD_AFFINITY2_999_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_999_LEN    8
#define GICD_REGS_GICD_AFFINITY1_999_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_999_LEN    8
#define GICD_REGS_GICD_AFFINITY0_999_OFFSET 0

#define GICD_REGS_GICD_IRM_1000_LEN          1
#define GICD_REGS_GICD_IRM_1000_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1000_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1000_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1000_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1000_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1000_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1000_OFFSET 0

#define GICD_REGS_GICD_IRM_1001_LEN          1
#define GICD_REGS_GICD_IRM_1001_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1001_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1001_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1001_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1001_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1001_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1001_OFFSET 0

#define GICD_REGS_GICD_IRM_1002_LEN          1
#define GICD_REGS_GICD_IRM_1002_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1002_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1002_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1002_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1002_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1002_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1002_OFFSET 0

#define GICD_REGS_GICD_IRM_1003_LEN          1
#define GICD_REGS_GICD_IRM_1003_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1003_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1003_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1003_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1003_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1003_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1003_OFFSET 0

#define GICD_REGS_GICD_IRM_1004_LEN          1
#define GICD_REGS_GICD_IRM_1004_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1004_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1004_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1004_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1004_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1004_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1004_OFFSET 0

#define GICD_REGS_GICD_IRM_1005_LEN          1
#define GICD_REGS_GICD_IRM_1005_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1005_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1005_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1005_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1005_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1005_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1005_OFFSET 0

#define GICD_REGS_GICD_IRM_1006_LEN          1
#define GICD_REGS_GICD_IRM_1006_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1006_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1006_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1006_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1006_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1006_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1006_OFFSET 0

#define GICD_REGS_GICD_IRM_1007_LEN          1
#define GICD_REGS_GICD_IRM_1007_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1007_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1007_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1007_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1007_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1007_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1007_OFFSET 0

#define GICD_REGS_GICD_IRM_1008_LEN          1
#define GICD_REGS_GICD_IRM_1008_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1008_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1008_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1008_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1008_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1008_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1008_OFFSET 0

#define GICD_REGS_GICD_IRM_1009_LEN          1
#define GICD_REGS_GICD_IRM_1009_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1009_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1009_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1009_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1009_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1009_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1009_OFFSET 0

#define GICD_REGS_GICD_IRM_1010_LEN          1
#define GICD_REGS_GICD_IRM_1010_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1010_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1010_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1010_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1010_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1010_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1010_OFFSET 0

#define GICD_REGS_GICD_IRM_1011_LEN          1
#define GICD_REGS_GICD_IRM_1011_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1011_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1011_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1011_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1011_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1011_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1011_OFFSET 0

#define GICD_REGS_GICD_IRM_1012_LEN          1
#define GICD_REGS_GICD_IRM_1012_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1012_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1012_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1012_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1012_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1012_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1012_OFFSET 0

#define GICD_REGS_GICD_IRM_1013_LEN          1
#define GICD_REGS_GICD_IRM_1013_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1013_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1013_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1013_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1013_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1013_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1013_OFFSET 0

#define GICD_REGS_GICD_IRM_1014_LEN          1
#define GICD_REGS_GICD_IRM_1014_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1014_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1014_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1014_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1014_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1014_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1014_OFFSET 0

#define GICD_REGS_GICD_IRM_1015_LEN          1
#define GICD_REGS_GICD_IRM_1015_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1015_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1015_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1015_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1015_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1015_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1015_OFFSET 0

#define GICD_REGS_GICD_IRM_1016_LEN          1
#define GICD_REGS_GICD_IRM_1016_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1016_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1016_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1016_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1016_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1016_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1016_OFFSET 0

#define GICD_REGS_GICD_IRM_1017_LEN          1
#define GICD_REGS_GICD_IRM_1017_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1017_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1017_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1017_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1017_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1017_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1017_OFFSET 0

#define GICD_REGS_GICD_IRM_1018_LEN          1
#define GICD_REGS_GICD_IRM_1018_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1018_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1018_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1018_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1018_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1018_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1018_OFFSET 0

#define GICD_REGS_GICD_IRM_1019_LEN          1
#define GICD_REGS_GICD_IRM_1019_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1019_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1019_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1019_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1019_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1019_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1019_OFFSET 0

#define GICD_REGS_GICD_IRM_1020_LEN          1
#define GICD_REGS_GICD_IRM_1020_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1020_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1020_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1020_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1020_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1020_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1020_OFFSET 0

#define GICD_REGS_GICD_IRM_1021_LEN          1
#define GICD_REGS_GICD_IRM_1021_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1021_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1021_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1021_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1021_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1021_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1021_OFFSET 0

#define GICD_REGS_GICD_IRM_1022_LEN          1
#define GICD_REGS_GICD_IRM_1022_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1022_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1022_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1022_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1022_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1022_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1022_OFFSET 0

#define GICD_REGS_GICD_IRM_1023_LEN          1
#define GICD_REGS_GICD_IRM_1023_OFFSET       31
#define GICD_REGS_GICD_AFFINITY2_1023_LEN    8
#define GICD_REGS_GICD_AFFINITY2_1023_OFFSET 16
#define GICD_REGS_GICD_AFFINITY1_1023_LEN    8
#define GICD_REGS_GICD_AFFINITY1_1023_OFFSET 8
#define GICD_REGS_GICD_AFFINITY0_1023_LEN    8
#define GICD_REGS_GICD_AFFINITY0_1023_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_0_LEN    8
#define GICD_REGS_GICD_AFFINITY3_0_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_2_LEN    8
#define GICD_REGS_GICD_AFFINITY3_2_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_3_LEN    8
#define GICD_REGS_GICD_AFFINITY3_3_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_4_LEN    8
#define GICD_REGS_GICD_AFFINITY3_4_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_5_LEN    8
#define GICD_REGS_GICD_AFFINITY3_5_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_6_LEN    8
#define GICD_REGS_GICD_AFFINITY3_6_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_7_LEN    8
#define GICD_REGS_GICD_AFFINITY3_7_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_8_LEN    8
#define GICD_REGS_GICD_AFFINITY3_8_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_9_LEN    8
#define GICD_REGS_GICD_AFFINITY3_9_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_10_LEN    8
#define GICD_REGS_GICD_AFFINITY3_10_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_11_LEN    8
#define GICD_REGS_GICD_AFFINITY3_11_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_12_LEN    8
#define GICD_REGS_GICD_AFFINITY3_12_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_13_LEN    8
#define GICD_REGS_GICD_AFFINITY3_13_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_14_LEN    8
#define GICD_REGS_GICD_AFFINITY3_14_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_15_LEN    8
#define GICD_REGS_GICD_AFFINITY3_15_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_16_LEN    8
#define GICD_REGS_GICD_AFFINITY3_16_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_17_LEN    8
#define GICD_REGS_GICD_AFFINITY3_17_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_18_LEN    8
#define GICD_REGS_GICD_AFFINITY3_18_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_19_LEN    8
#define GICD_REGS_GICD_AFFINITY3_19_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_20_LEN    8
#define GICD_REGS_GICD_AFFINITY3_20_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_21_LEN    8
#define GICD_REGS_GICD_AFFINITY3_21_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_22_LEN    8
#define GICD_REGS_GICD_AFFINITY3_22_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_23_LEN    8
#define GICD_REGS_GICD_AFFINITY3_23_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_24_LEN    8
#define GICD_REGS_GICD_AFFINITY3_24_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_25_LEN    8
#define GICD_REGS_GICD_AFFINITY3_25_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_26_LEN    8
#define GICD_REGS_GICD_AFFINITY3_26_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_27_LEN    8
#define GICD_REGS_GICD_AFFINITY3_27_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_28_LEN    8
#define GICD_REGS_GICD_AFFINITY3_28_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_29_LEN    8
#define GICD_REGS_GICD_AFFINITY3_29_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_30_LEN    8
#define GICD_REGS_GICD_AFFINITY3_30_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_31_LEN    8
#define GICD_REGS_GICD_AFFINITY3_31_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_32_LEN    8
#define GICD_REGS_GICD_AFFINITY3_32_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_33_LEN    8
#define GICD_REGS_GICD_AFFINITY3_33_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_34_LEN    8
#define GICD_REGS_GICD_AFFINITY3_34_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_35_LEN    8
#define GICD_REGS_GICD_AFFINITY3_35_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_36_LEN    8
#define GICD_REGS_GICD_AFFINITY3_36_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_37_LEN    8
#define GICD_REGS_GICD_AFFINITY3_37_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_38_LEN    8
#define GICD_REGS_GICD_AFFINITY3_38_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_39_LEN    8
#define GICD_REGS_GICD_AFFINITY3_39_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_40_LEN    8
#define GICD_REGS_GICD_AFFINITY3_40_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_41_LEN    8
#define GICD_REGS_GICD_AFFINITY3_41_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_42_LEN    8
#define GICD_REGS_GICD_AFFINITY3_42_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_43_LEN    8
#define GICD_REGS_GICD_AFFINITY3_43_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_44_LEN    8
#define GICD_REGS_GICD_AFFINITY3_44_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_45_LEN    8
#define GICD_REGS_GICD_AFFINITY3_45_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_46_LEN    8
#define GICD_REGS_GICD_AFFINITY3_46_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_47_LEN    8
#define GICD_REGS_GICD_AFFINITY3_47_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_48_LEN    8
#define GICD_REGS_GICD_AFFINITY3_48_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_49_LEN    8
#define GICD_REGS_GICD_AFFINITY3_49_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_50_LEN    8
#define GICD_REGS_GICD_AFFINITY3_50_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_51_LEN    8
#define GICD_REGS_GICD_AFFINITY3_51_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_52_LEN    8
#define GICD_REGS_GICD_AFFINITY3_52_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_53_LEN    8
#define GICD_REGS_GICD_AFFINITY3_53_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_54_LEN    8
#define GICD_REGS_GICD_AFFINITY3_54_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_55_LEN    8
#define GICD_REGS_GICD_AFFINITY3_55_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_56_LEN    8
#define GICD_REGS_GICD_AFFINITY3_56_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_57_LEN    8
#define GICD_REGS_GICD_AFFINITY3_57_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_58_LEN    8
#define GICD_REGS_GICD_AFFINITY3_58_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_59_LEN    8
#define GICD_REGS_GICD_AFFINITY3_59_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_60_LEN    8
#define GICD_REGS_GICD_AFFINITY3_60_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_61_LEN    8
#define GICD_REGS_GICD_AFFINITY3_61_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_62_LEN    8
#define GICD_REGS_GICD_AFFINITY3_62_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_63_LEN    8
#define GICD_REGS_GICD_AFFINITY3_63_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_64_LEN    8
#define GICD_REGS_GICD_AFFINITY3_64_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_65_LEN    8
#define GICD_REGS_GICD_AFFINITY3_65_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_66_LEN    8
#define GICD_REGS_GICD_AFFINITY3_66_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_67_LEN    8
#define GICD_REGS_GICD_AFFINITY3_67_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_68_LEN    8
#define GICD_REGS_GICD_AFFINITY3_68_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_69_LEN    8
#define GICD_REGS_GICD_AFFINITY3_69_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_70_LEN    8
#define GICD_REGS_GICD_AFFINITY3_70_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_71_LEN    8
#define GICD_REGS_GICD_AFFINITY3_71_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_72_LEN    8
#define GICD_REGS_GICD_AFFINITY3_72_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_73_LEN    8
#define GICD_REGS_GICD_AFFINITY3_73_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_74_LEN    8
#define GICD_REGS_GICD_AFFINITY3_74_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_75_LEN    8
#define GICD_REGS_GICD_AFFINITY3_75_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_76_LEN    8
#define GICD_REGS_GICD_AFFINITY3_76_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_77_LEN    8
#define GICD_REGS_GICD_AFFINITY3_77_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_78_LEN    8
#define GICD_REGS_GICD_AFFINITY3_78_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_79_LEN    8
#define GICD_REGS_GICD_AFFINITY3_79_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_80_LEN    8
#define GICD_REGS_GICD_AFFINITY3_80_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_81_LEN    8
#define GICD_REGS_GICD_AFFINITY3_81_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_82_LEN    8
#define GICD_REGS_GICD_AFFINITY3_82_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_83_LEN    8
#define GICD_REGS_GICD_AFFINITY3_83_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_84_LEN    8
#define GICD_REGS_GICD_AFFINITY3_84_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_85_LEN    8
#define GICD_REGS_GICD_AFFINITY3_85_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_86_LEN    8
#define GICD_REGS_GICD_AFFINITY3_86_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_87_LEN    8
#define GICD_REGS_GICD_AFFINITY3_87_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_88_LEN    8
#define GICD_REGS_GICD_AFFINITY3_88_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_89_LEN    8
#define GICD_REGS_GICD_AFFINITY3_89_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_90_LEN    8
#define GICD_REGS_GICD_AFFINITY3_90_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_91_LEN    8
#define GICD_REGS_GICD_AFFINITY3_91_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_92_LEN    8
#define GICD_REGS_GICD_AFFINITY3_92_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_93_LEN    8
#define GICD_REGS_GICD_AFFINITY3_93_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_94_LEN    8
#define GICD_REGS_GICD_AFFINITY3_94_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_95_LEN    8
#define GICD_REGS_GICD_AFFINITY3_95_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_96_LEN    8
#define GICD_REGS_GICD_AFFINITY3_96_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_97_LEN    8
#define GICD_REGS_GICD_AFFINITY3_97_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_98_LEN    8
#define GICD_REGS_GICD_AFFINITY3_98_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_99_LEN    8
#define GICD_REGS_GICD_AFFINITY3_99_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_100_LEN    8
#define GICD_REGS_GICD_AFFINITY3_100_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_101_LEN    8
#define GICD_REGS_GICD_AFFINITY3_101_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_102_LEN    8
#define GICD_REGS_GICD_AFFINITY3_102_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_103_LEN    8
#define GICD_REGS_GICD_AFFINITY3_103_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_104_LEN    8
#define GICD_REGS_GICD_AFFINITY3_104_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_105_LEN    8
#define GICD_REGS_GICD_AFFINITY3_105_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_106_LEN    8
#define GICD_REGS_GICD_AFFINITY3_106_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_107_LEN    8
#define GICD_REGS_GICD_AFFINITY3_107_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_108_LEN    8
#define GICD_REGS_GICD_AFFINITY3_108_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_109_LEN    8
#define GICD_REGS_GICD_AFFINITY3_109_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_110_LEN    8
#define GICD_REGS_GICD_AFFINITY3_110_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_111_LEN    8
#define GICD_REGS_GICD_AFFINITY3_111_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_112_LEN    8
#define GICD_REGS_GICD_AFFINITY3_112_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_113_LEN    8
#define GICD_REGS_GICD_AFFINITY3_113_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_114_LEN    8
#define GICD_REGS_GICD_AFFINITY3_114_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_115_LEN    8
#define GICD_REGS_GICD_AFFINITY3_115_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_116_LEN    8
#define GICD_REGS_GICD_AFFINITY3_116_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_117_LEN    8
#define GICD_REGS_GICD_AFFINITY3_117_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_118_LEN    8
#define GICD_REGS_GICD_AFFINITY3_118_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_119_LEN    8
#define GICD_REGS_GICD_AFFINITY3_119_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_120_LEN    8
#define GICD_REGS_GICD_AFFINITY3_120_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_121_LEN    8
#define GICD_REGS_GICD_AFFINITY3_121_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_122_LEN    8
#define GICD_REGS_GICD_AFFINITY3_122_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_123_LEN    8
#define GICD_REGS_GICD_AFFINITY3_123_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_124_LEN    8
#define GICD_REGS_GICD_AFFINITY3_124_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_125_LEN    8
#define GICD_REGS_GICD_AFFINITY3_125_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_126_LEN    8
#define GICD_REGS_GICD_AFFINITY3_126_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_127_LEN    8
#define GICD_REGS_GICD_AFFINITY3_127_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_128_LEN    8
#define GICD_REGS_GICD_AFFINITY3_128_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_129_LEN    8
#define GICD_REGS_GICD_AFFINITY3_129_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_130_LEN    8
#define GICD_REGS_GICD_AFFINITY3_130_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_131_LEN    8
#define GICD_REGS_GICD_AFFINITY3_131_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_132_LEN    8
#define GICD_REGS_GICD_AFFINITY3_132_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_133_LEN    8
#define GICD_REGS_GICD_AFFINITY3_133_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_134_LEN    8
#define GICD_REGS_GICD_AFFINITY3_134_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_135_LEN    8
#define GICD_REGS_GICD_AFFINITY3_135_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_136_LEN    8
#define GICD_REGS_GICD_AFFINITY3_136_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_137_LEN    8
#define GICD_REGS_GICD_AFFINITY3_137_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_138_LEN    8
#define GICD_REGS_GICD_AFFINITY3_138_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_139_LEN    8
#define GICD_REGS_GICD_AFFINITY3_139_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_140_LEN    8
#define GICD_REGS_GICD_AFFINITY3_140_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_141_LEN    8
#define GICD_REGS_GICD_AFFINITY3_141_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_142_LEN    8
#define GICD_REGS_GICD_AFFINITY3_142_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_143_LEN    8
#define GICD_REGS_GICD_AFFINITY3_143_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_144_LEN    8
#define GICD_REGS_GICD_AFFINITY3_144_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_145_LEN    8
#define GICD_REGS_GICD_AFFINITY3_145_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_146_LEN    8
#define GICD_REGS_GICD_AFFINITY3_146_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_147_LEN    8
#define GICD_REGS_GICD_AFFINITY3_147_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_148_LEN    8
#define GICD_REGS_GICD_AFFINITY3_148_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_149_LEN    8
#define GICD_REGS_GICD_AFFINITY3_149_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_150_LEN    8
#define GICD_REGS_GICD_AFFINITY3_150_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_151_LEN    8
#define GICD_REGS_GICD_AFFINITY3_151_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_152_LEN    8
#define GICD_REGS_GICD_AFFINITY3_152_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_153_LEN    8
#define GICD_REGS_GICD_AFFINITY3_153_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_154_LEN    8
#define GICD_REGS_GICD_AFFINITY3_154_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_155_LEN    8
#define GICD_REGS_GICD_AFFINITY3_155_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_156_LEN    8
#define GICD_REGS_GICD_AFFINITY3_156_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_157_LEN    8
#define GICD_REGS_GICD_AFFINITY3_157_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_158_LEN    8
#define GICD_REGS_GICD_AFFINITY3_158_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_159_LEN    8
#define GICD_REGS_GICD_AFFINITY3_159_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_160_LEN    8
#define GICD_REGS_GICD_AFFINITY3_160_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_161_LEN    8
#define GICD_REGS_GICD_AFFINITY3_161_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_162_LEN    8
#define GICD_REGS_GICD_AFFINITY3_162_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_163_LEN    8
#define GICD_REGS_GICD_AFFINITY3_163_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_164_LEN    8
#define GICD_REGS_GICD_AFFINITY3_164_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_165_LEN    8
#define GICD_REGS_GICD_AFFINITY3_165_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_166_LEN    8
#define GICD_REGS_GICD_AFFINITY3_166_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_167_LEN    8
#define GICD_REGS_GICD_AFFINITY3_167_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_168_LEN    8
#define GICD_REGS_GICD_AFFINITY3_168_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_169_LEN    8
#define GICD_REGS_GICD_AFFINITY3_169_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_170_LEN    8
#define GICD_REGS_GICD_AFFINITY3_170_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_171_LEN    8
#define GICD_REGS_GICD_AFFINITY3_171_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_172_LEN    8
#define GICD_REGS_GICD_AFFINITY3_172_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_173_LEN    8
#define GICD_REGS_GICD_AFFINITY3_173_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_174_LEN    8
#define GICD_REGS_GICD_AFFINITY3_174_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_175_LEN    8
#define GICD_REGS_GICD_AFFINITY3_175_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_176_LEN    8
#define GICD_REGS_GICD_AFFINITY3_176_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_177_LEN    8
#define GICD_REGS_GICD_AFFINITY3_177_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_178_LEN    8
#define GICD_REGS_GICD_AFFINITY3_178_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_179_LEN    8
#define GICD_REGS_GICD_AFFINITY3_179_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_180_LEN    8
#define GICD_REGS_GICD_AFFINITY3_180_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_181_LEN    8
#define GICD_REGS_GICD_AFFINITY3_181_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_182_LEN    8
#define GICD_REGS_GICD_AFFINITY3_182_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_183_LEN    8
#define GICD_REGS_GICD_AFFINITY3_183_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_184_LEN    8
#define GICD_REGS_GICD_AFFINITY3_184_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_185_LEN    8
#define GICD_REGS_GICD_AFFINITY3_185_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_186_LEN    8
#define GICD_REGS_GICD_AFFINITY3_186_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_187_LEN    8
#define GICD_REGS_GICD_AFFINITY3_187_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_188_LEN    8
#define GICD_REGS_GICD_AFFINITY3_188_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_189_LEN    8
#define GICD_REGS_GICD_AFFINITY3_189_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_190_LEN    8
#define GICD_REGS_GICD_AFFINITY3_190_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_191_LEN    8
#define GICD_REGS_GICD_AFFINITY3_191_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_192_LEN    8
#define GICD_REGS_GICD_AFFINITY3_192_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_193_LEN    8
#define GICD_REGS_GICD_AFFINITY3_193_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_194_LEN    8
#define GICD_REGS_GICD_AFFINITY3_194_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_195_LEN    8
#define GICD_REGS_GICD_AFFINITY3_195_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_196_LEN    8
#define GICD_REGS_GICD_AFFINITY3_196_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_197_LEN    8
#define GICD_REGS_GICD_AFFINITY3_197_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_198_LEN    8
#define GICD_REGS_GICD_AFFINITY3_198_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_199_LEN    8
#define GICD_REGS_GICD_AFFINITY3_199_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_200_LEN    8
#define GICD_REGS_GICD_AFFINITY3_200_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_201_LEN    8
#define GICD_REGS_GICD_AFFINITY3_201_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_202_LEN    8
#define GICD_REGS_GICD_AFFINITY3_202_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_203_LEN    8
#define GICD_REGS_GICD_AFFINITY3_203_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_204_LEN    8
#define GICD_REGS_GICD_AFFINITY3_204_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_205_LEN    8
#define GICD_REGS_GICD_AFFINITY3_205_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_206_LEN    8
#define GICD_REGS_GICD_AFFINITY3_206_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_207_LEN    8
#define GICD_REGS_GICD_AFFINITY3_207_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_208_LEN    8
#define GICD_REGS_GICD_AFFINITY3_208_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_209_LEN    8
#define GICD_REGS_GICD_AFFINITY3_209_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_210_LEN    8
#define GICD_REGS_GICD_AFFINITY3_210_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_211_LEN    8
#define GICD_REGS_GICD_AFFINITY3_211_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_212_LEN    8
#define GICD_REGS_GICD_AFFINITY3_212_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_213_LEN    8
#define GICD_REGS_GICD_AFFINITY3_213_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_214_LEN    8
#define GICD_REGS_GICD_AFFINITY3_214_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_215_LEN    8
#define GICD_REGS_GICD_AFFINITY3_215_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_216_LEN    8
#define GICD_REGS_GICD_AFFINITY3_216_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_217_LEN    8
#define GICD_REGS_GICD_AFFINITY3_217_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_218_LEN    8
#define GICD_REGS_GICD_AFFINITY3_218_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_219_LEN    8
#define GICD_REGS_GICD_AFFINITY3_219_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_220_LEN    8
#define GICD_REGS_GICD_AFFINITY3_220_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_221_LEN    8
#define GICD_REGS_GICD_AFFINITY3_221_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_222_LEN    8
#define GICD_REGS_GICD_AFFINITY3_222_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_223_LEN    8
#define GICD_REGS_GICD_AFFINITY3_223_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_224_LEN    8
#define GICD_REGS_GICD_AFFINITY3_224_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_225_LEN    8
#define GICD_REGS_GICD_AFFINITY3_225_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_226_LEN    8
#define GICD_REGS_GICD_AFFINITY3_226_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_227_LEN    8
#define GICD_REGS_GICD_AFFINITY3_227_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_228_LEN    8
#define GICD_REGS_GICD_AFFINITY3_228_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_229_LEN    8
#define GICD_REGS_GICD_AFFINITY3_229_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_230_LEN    8
#define GICD_REGS_GICD_AFFINITY3_230_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_231_LEN    8
#define GICD_REGS_GICD_AFFINITY3_231_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_232_LEN    8
#define GICD_REGS_GICD_AFFINITY3_232_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_233_LEN    8
#define GICD_REGS_GICD_AFFINITY3_233_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_234_LEN    8
#define GICD_REGS_GICD_AFFINITY3_234_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_235_LEN    8
#define GICD_REGS_GICD_AFFINITY3_235_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_236_LEN    8
#define GICD_REGS_GICD_AFFINITY3_236_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_237_LEN    8
#define GICD_REGS_GICD_AFFINITY3_237_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_238_LEN    8
#define GICD_REGS_GICD_AFFINITY3_238_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_239_LEN    8
#define GICD_REGS_GICD_AFFINITY3_239_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_240_LEN    8
#define GICD_REGS_GICD_AFFINITY3_240_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_241_LEN    8
#define GICD_REGS_GICD_AFFINITY3_241_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_242_LEN    8
#define GICD_REGS_GICD_AFFINITY3_242_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_243_LEN    8
#define GICD_REGS_GICD_AFFINITY3_243_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_244_LEN    8
#define GICD_REGS_GICD_AFFINITY3_244_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_245_LEN    8
#define GICD_REGS_GICD_AFFINITY3_245_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_246_LEN    8
#define GICD_REGS_GICD_AFFINITY3_246_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_247_LEN    8
#define GICD_REGS_GICD_AFFINITY3_247_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_248_LEN    8
#define GICD_REGS_GICD_AFFINITY3_248_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_249_LEN    8
#define GICD_REGS_GICD_AFFINITY3_249_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_250_LEN    8
#define GICD_REGS_GICD_AFFINITY3_250_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_251_LEN    8
#define GICD_REGS_GICD_AFFINITY3_251_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_252_LEN    8
#define GICD_REGS_GICD_AFFINITY3_252_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_253_LEN    8
#define GICD_REGS_GICD_AFFINITY3_253_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_254_LEN    8
#define GICD_REGS_GICD_AFFINITY3_254_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_255_LEN    8
#define GICD_REGS_GICD_AFFINITY3_255_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_256_LEN    8
#define GICD_REGS_GICD_AFFINITY3_256_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_257_LEN    8
#define GICD_REGS_GICD_AFFINITY3_257_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_258_LEN    8
#define GICD_REGS_GICD_AFFINITY3_258_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_259_LEN    8
#define GICD_REGS_GICD_AFFINITY3_259_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_260_LEN    8
#define GICD_REGS_GICD_AFFINITY3_260_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_261_LEN    8
#define GICD_REGS_GICD_AFFINITY3_261_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_262_LEN    8
#define GICD_REGS_GICD_AFFINITY3_262_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_263_LEN    8
#define GICD_REGS_GICD_AFFINITY3_263_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_264_LEN    8
#define GICD_REGS_GICD_AFFINITY3_264_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_265_LEN    8
#define GICD_REGS_GICD_AFFINITY3_265_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_266_LEN    8
#define GICD_REGS_GICD_AFFINITY3_266_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_267_LEN    8
#define GICD_REGS_GICD_AFFINITY3_267_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_268_LEN    8
#define GICD_REGS_GICD_AFFINITY3_268_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_269_LEN    8
#define GICD_REGS_GICD_AFFINITY3_269_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_270_LEN    8
#define GICD_REGS_GICD_AFFINITY3_270_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_271_LEN    8
#define GICD_REGS_GICD_AFFINITY3_271_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_272_LEN    8
#define GICD_REGS_GICD_AFFINITY3_272_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_273_LEN    8
#define GICD_REGS_GICD_AFFINITY3_273_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_274_LEN    8
#define GICD_REGS_GICD_AFFINITY3_274_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_275_LEN    8
#define GICD_REGS_GICD_AFFINITY3_275_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_276_LEN    8
#define GICD_REGS_GICD_AFFINITY3_276_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_277_LEN    8
#define GICD_REGS_GICD_AFFINITY3_277_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_278_LEN    8
#define GICD_REGS_GICD_AFFINITY3_278_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_279_LEN    8
#define GICD_REGS_GICD_AFFINITY3_279_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_280_LEN    8
#define GICD_REGS_GICD_AFFINITY3_280_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_281_LEN    8
#define GICD_REGS_GICD_AFFINITY3_281_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_282_LEN    8
#define GICD_REGS_GICD_AFFINITY3_282_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_283_LEN    8
#define GICD_REGS_GICD_AFFINITY3_283_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_284_LEN    8
#define GICD_REGS_GICD_AFFINITY3_284_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_285_LEN    8
#define GICD_REGS_GICD_AFFINITY3_285_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_286_LEN    8
#define GICD_REGS_GICD_AFFINITY3_286_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_287_LEN    8
#define GICD_REGS_GICD_AFFINITY3_287_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_288_LEN    8
#define GICD_REGS_GICD_AFFINITY3_288_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_289_LEN    8
#define GICD_REGS_GICD_AFFINITY3_289_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_290_LEN    8
#define GICD_REGS_GICD_AFFINITY3_290_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_291_LEN    8
#define GICD_REGS_GICD_AFFINITY3_291_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_292_LEN    8
#define GICD_REGS_GICD_AFFINITY3_292_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_293_LEN    8
#define GICD_REGS_GICD_AFFINITY3_293_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_294_LEN    8
#define GICD_REGS_GICD_AFFINITY3_294_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_295_LEN    8
#define GICD_REGS_GICD_AFFINITY3_295_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_296_LEN    8
#define GICD_REGS_GICD_AFFINITY3_296_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_297_LEN    8
#define GICD_REGS_GICD_AFFINITY3_297_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_298_LEN    8
#define GICD_REGS_GICD_AFFINITY3_298_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_299_LEN    8
#define GICD_REGS_GICD_AFFINITY3_299_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_300_LEN    8
#define GICD_REGS_GICD_AFFINITY3_300_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_301_LEN    8
#define GICD_REGS_GICD_AFFINITY3_301_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_302_LEN    8
#define GICD_REGS_GICD_AFFINITY3_302_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_303_LEN    8
#define GICD_REGS_GICD_AFFINITY3_303_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_304_LEN    8
#define GICD_REGS_GICD_AFFINITY3_304_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_305_LEN    8
#define GICD_REGS_GICD_AFFINITY3_305_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_306_LEN    8
#define GICD_REGS_GICD_AFFINITY3_306_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_307_LEN    8
#define GICD_REGS_GICD_AFFINITY3_307_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_308_LEN    8
#define GICD_REGS_GICD_AFFINITY3_308_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_309_LEN    8
#define GICD_REGS_GICD_AFFINITY3_309_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_310_LEN    8
#define GICD_REGS_GICD_AFFINITY3_310_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_311_LEN    8
#define GICD_REGS_GICD_AFFINITY3_311_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_312_LEN    8
#define GICD_REGS_GICD_AFFINITY3_312_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_313_LEN    8
#define GICD_REGS_GICD_AFFINITY3_313_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_314_LEN    8
#define GICD_REGS_GICD_AFFINITY3_314_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_315_LEN    8
#define GICD_REGS_GICD_AFFINITY3_315_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_316_LEN    8
#define GICD_REGS_GICD_AFFINITY3_316_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_317_LEN    8
#define GICD_REGS_GICD_AFFINITY3_317_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_318_LEN    8
#define GICD_REGS_GICD_AFFINITY3_318_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_319_LEN    8
#define GICD_REGS_GICD_AFFINITY3_319_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_320_LEN    8
#define GICD_REGS_GICD_AFFINITY3_320_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_321_LEN    8
#define GICD_REGS_GICD_AFFINITY3_321_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_322_LEN    8
#define GICD_REGS_GICD_AFFINITY3_322_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_323_LEN    8
#define GICD_REGS_GICD_AFFINITY3_323_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_324_LEN    8
#define GICD_REGS_GICD_AFFINITY3_324_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_325_LEN    8
#define GICD_REGS_GICD_AFFINITY3_325_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_326_LEN    8
#define GICD_REGS_GICD_AFFINITY3_326_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_327_LEN    8
#define GICD_REGS_GICD_AFFINITY3_327_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_328_LEN    8
#define GICD_REGS_GICD_AFFINITY3_328_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_329_LEN    8
#define GICD_REGS_GICD_AFFINITY3_329_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_330_LEN    8
#define GICD_REGS_GICD_AFFINITY3_330_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_331_LEN    8
#define GICD_REGS_GICD_AFFINITY3_331_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_332_LEN    8
#define GICD_REGS_GICD_AFFINITY3_332_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_333_LEN    8
#define GICD_REGS_GICD_AFFINITY3_333_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_334_LEN    8
#define GICD_REGS_GICD_AFFINITY3_334_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_335_LEN    8
#define GICD_REGS_GICD_AFFINITY3_335_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_336_LEN    8
#define GICD_REGS_GICD_AFFINITY3_336_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_337_LEN    8
#define GICD_REGS_GICD_AFFINITY3_337_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_338_LEN    8
#define GICD_REGS_GICD_AFFINITY3_338_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_339_LEN    8
#define GICD_REGS_GICD_AFFINITY3_339_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_340_LEN    8
#define GICD_REGS_GICD_AFFINITY3_340_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_341_LEN    8
#define GICD_REGS_GICD_AFFINITY3_341_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_342_LEN    8
#define GICD_REGS_GICD_AFFINITY3_342_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_343_LEN    8
#define GICD_REGS_GICD_AFFINITY3_343_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_344_LEN    8
#define GICD_REGS_GICD_AFFINITY3_344_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_345_LEN    8
#define GICD_REGS_GICD_AFFINITY3_345_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_346_LEN    8
#define GICD_REGS_GICD_AFFINITY3_346_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_347_LEN    8
#define GICD_REGS_GICD_AFFINITY3_347_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_348_LEN    8
#define GICD_REGS_GICD_AFFINITY3_348_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_349_LEN    8
#define GICD_REGS_GICD_AFFINITY3_349_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_350_LEN    8
#define GICD_REGS_GICD_AFFINITY3_350_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_351_LEN    8
#define GICD_REGS_GICD_AFFINITY3_351_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_352_LEN    8
#define GICD_REGS_GICD_AFFINITY3_352_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_353_LEN    8
#define GICD_REGS_GICD_AFFINITY3_353_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_354_LEN    8
#define GICD_REGS_GICD_AFFINITY3_354_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_355_LEN    8
#define GICD_REGS_GICD_AFFINITY3_355_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_356_LEN    8
#define GICD_REGS_GICD_AFFINITY3_356_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_357_LEN    8
#define GICD_REGS_GICD_AFFINITY3_357_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_358_LEN    8
#define GICD_REGS_GICD_AFFINITY3_358_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_359_LEN    8
#define GICD_REGS_GICD_AFFINITY3_359_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_360_LEN    8
#define GICD_REGS_GICD_AFFINITY3_360_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_361_LEN    8
#define GICD_REGS_GICD_AFFINITY3_361_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_362_LEN    8
#define GICD_REGS_GICD_AFFINITY3_362_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_363_LEN    8
#define GICD_REGS_GICD_AFFINITY3_363_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_364_LEN    8
#define GICD_REGS_GICD_AFFINITY3_364_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_365_LEN    8
#define GICD_REGS_GICD_AFFINITY3_365_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_366_LEN    8
#define GICD_REGS_GICD_AFFINITY3_366_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_367_LEN    8
#define GICD_REGS_GICD_AFFINITY3_367_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_368_LEN    8
#define GICD_REGS_GICD_AFFINITY3_368_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_369_LEN    8
#define GICD_REGS_GICD_AFFINITY3_369_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_370_LEN    8
#define GICD_REGS_GICD_AFFINITY3_370_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_371_LEN    8
#define GICD_REGS_GICD_AFFINITY3_371_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_372_LEN    8
#define GICD_REGS_GICD_AFFINITY3_372_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_373_LEN    8
#define GICD_REGS_GICD_AFFINITY3_373_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_374_LEN    8
#define GICD_REGS_GICD_AFFINITY3_374_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_375_LEN    8
#define GICD_REGS_GICD_AFFINITY3_375_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_376_LEN    8
#define GICD_REGS_GICD_AFFINITY3_376_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_377_LEN    8
#define GICD_REGS_GICD_AFFINITY3_377_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_378_LEN    8
#define GICD_REGS_GICD_AFFINITY3_378_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_379_LEN    8
#define GICD_REGS_GICD_AFFINITY3_379_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_380_LEN    8
#define GICD_REGS_GICD_AFFINITY3_380_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_381_LEN    8
#define GICD_REGS_GICD_AFFINITY3_381_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_382_LEN    8
#define GICD_REGS_GICD_AFFINITY3_382_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_383_LEN    8
#define GICD_REGS_GICD_AFFINITY3_383_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_384_LEN    8
#define GICD_REGS_GICD_AFFINITY3_384_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_385_LEN    8
#define GICD_REGS_GICD_AFFINITY3_385_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_386_LEN    8
#define GICD_REGS_GICD_AFFINITY3_386_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_387_LEN    8
#define GICD_REGS_GICD_AFFINITY3_387_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_388_LEN    8
#define GICD_REGS_GICD_AFFINITY3_388_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_389_LEN    8
#define GICD_REGS_GICD_AFFINITY3_389_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_390_LEN    8
#define GICD_REGS_GICD_AFFINITY3_390_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_391_LEN    8
#define GICD_REGS_GICD_AFFINITY3_391_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_392_LEN    8
#define GICD_REGS_GICD_AFFINITY3_392_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_393_LEN    8
#define GICD_REGS_GICD_AFFINITY3_393_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_394_LEN    8
#define GICD_REGS_GICD_AFFINITY3_394_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_395_LEN    8
#define GICD_REGS_GICD_AFFINITY3_395_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_396_LEN    8
#define GICD_REGS_GICD_AFFINITY3_396_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_397_LEN    8
#define GICD_REGS_GICD_AFFINITY3_397_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_398_LEN    8
#define GICD_REGS_GICD_AFFINITY3_398_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_399_LEN    8
#define GICD_REGS_GICD_AFFINITY3_399_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_400_LEN    8
#define GICD_REGS_GICD_AFFINITY3_400_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_401_LEN    8
#define GICD_REGS_GICD_AFFINITY3_401_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_402_LEN    8
#define GICD_REGS_GICD_AFFINITY3_402_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_403_LEN    8
#define GICD_REGS_GICD_AFFINITY3_403_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_404_LEN    8
#define GICD_REGS_GICD_AFFINITY3_404_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_405_LEN    8
#define GICD_REGS_GICD_AFFINITY3_405_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_406_LEN    8
#define GICD_REGS_GICD_AFFINITY3_406_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_407_LEN    8
#define GICD_REGS_GICD_AFFINITY3_407_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_408_LEN    8
#define GICD_REGS_GICD_AFFINITY3_408_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_409_LEN    8
#define GICD_REGS_GICD_AFFINITY3_409_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_410_LEN    8
#define GICD_REGS_GICD_AFFINITY3_410_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_411_LEN    8
#define GICD_REGS_GICD_AFFINITY3_411_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_412_LEN    8
#define GICD_REGS_GICD_AFFINITY3_412_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_413_LEN    8
#define GICD_REGS_GICD_AFFINITY3_413_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_414_LEN    8
#define GICD_REGS_GICD_AFFINITY3_414_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_415_LEN    8
#define GICD_REGS_GICD_AFFINITY3_415_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_416_LEN    8
#define GICD_REGS_GICD_AFFINITY3_416_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_417_LEN    8
#define GICD_REGS_GICD_AFFINITY3_417_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_418_LEN    8
#define GICD_REGS_GICD_AFFINITY3_418_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_419_LEN    8
#define GICD_REGS_GICD_AFFINITY3_419_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_420_LEN    8
#define GICD_REGS_GICD_AFFINITY3_420_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_421_LEN    8
#define GICD_REGS_GICD_AFFINITY3_421_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_422_LEN    8
#define GICD_REGS_GICD_AFFINITY3_422_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_423_LEN    8
#define GICD_REGS_GICD_AFFINITY3_423_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_424_LEN    8
#define GICD_REGS_GICD_AFFINITY3_424_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_425_LEN    8
#define GICD_REGS_GICD_AFFINITY3_425_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_426_LEN    8
#define GICD_REGS_GICD_AFFINITY3_426_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_427_LEN    8
#define GICD_REGS_GICD_AFFINITY3_427_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_428_LEN    8
#define GICD_REGS_GICD_AFFINITY3_428_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_429_LEN    8
#define GICD_REGS_GICD_AFFINITY3_429_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_430_LEN    8
#define GICD_REGS_GICD_AFFINITY3_430_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_431_LEN    8
#define GICD_REGS_GICD_AFFINITY3_431_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_432_LEN    8
#define GICD_REGS_GICD_AFFINITY3_432_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_433_LEN    8
#define GICD_REGS_GICD_AFFINITY3_433_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_434_LEN    8
#define GICD_REGS_GICD_AFFINITY3_434_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_435_LEN    8
#define GICD_REGS_GICD_AFFINITY3_435_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_436_LEN    8
#define GICD_REGS_GICD_AFFINITY3_436_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_437_LEN    8
#define GICD_REGS_GICD_AFFINITY3_437_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_438_LEN    8
#define GICD_REGS_GICD_AFFINITY3_438_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_439_LEN    8
#define GICD_REGS_GICD_AFFINITY3_439_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_440_LEN    8
#define GICD_REGS_GICD_AFFINITY3_440_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_441_LEN    8
#define GICD_REGS_GICD_AFFINITY3_441_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_442_LEN    8
#define GICD_REGS_GICD_AFFINITY3_442_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_443_LEN    8
#define GICD_REGS_GICD_AFFINITY3_443_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_444_LEN    8
#define GICD_REGS_GICD_AFFINITY3_444_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_445_LEN    8
#define GICD_REGS_GICD_AFFINITY3_445_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_446_LEN    8
#define GICD_REGS_GICD_AFFINITY3_446_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_447_LEN    8
#define GICD_REGS_GICD_AFFINITY3_447_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_448_LEN    8
#define GICD_REGS_GICD_AFFINITY3_448_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_449_LEN    8
#define GICD_REGS_GICD_AFFINITY3_449_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_450_LEN    8
#define GICD_REGS_GICD_AFFINITY3_450_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_451_LEN    8
#define GICD_REGS_GICD_AFFINITY3_451_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_452_LEN    8
#define GICD_REGS_GICD_AFFINITY3_452_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_453_LEN    8
#define GICD_REGS_GICD_AFFINITY3_453_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_454_LEN    8
#define GICD_REGS_GICD_AFFINITY3_454_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_455_LEN    8
#define GICD_REGS_GICD_AFFINITY3_455_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_456_LEN    8
#define GICD_REGS_GICD_AFFINITY3_456_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_457_LEN    8
#define GICD_REGS_GICD_AFFINITY3_457_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_458_LEN    8
#define GICD_REGS_GICD_AFFINITY3_458_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_459_LEN    8
#define GICD_REGS_GICD_AFFINITY3_459_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_460_LEN    8
#define GICD_REGS_GICD_AFFINITY3_460_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_461_LEN    8
#define GICD_REGS_GICD_AFFINITY3_461_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_462_LEN    8
#define GICD_REGS_GICD_AFFINITY3_462_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_463_LEN    8
#define GICD_REGS_GICD_AFFINITY3_463_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_464_LEN    8
#define GICD_REGS_GICD_AFFINITY3_464_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_465_LEN    8
#define GICD_REGS_GICD_AFFINITY3_465_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_466_LEN    8
#define GICD_REGS_GICD_AFFINITY3_466_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_467_LEN    8
#define GICD_REGS_GICD_AFFINITY3_467_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_468_LEN    8
#define GICD_REGS_GICD_AFFINITY3_468_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_469_LEN    8
#define GICD_REGS_GICD_AFFINITY3_469_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_470_LEN    8
#define GICD_REGS_GICD_AFFINITY3_470_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_471_LEN    8
#define GICD_REGS_GICD_AFFINITY3_471_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_472_LEN    8
#define GICD_REGS_GICD_AFFINITY3_472_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_473_LEN    8
#define GICD_REGS_GICD_AFFINITY3_473_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_474_LEN    8
#define GICD_REGS_GICD_AFFINITY3_474_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_475_LEN    8
#define GICD_REGS_GICD_AFFINITY3_475_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_476_LEN    8
#define GICD_REGS_GICD_AFFINITY3_476_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_477_LEN    8
#define GICD_REGS_GICD_AFFINITY3_477_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_478_LEN    8
#define GICD_REGS_GICD_AFFINITY3_478_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_479_LEN    8
#define GICD_REGS_GICD_AFFINITY3_479_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_480_LEN    8
#define GICD_REGS_GICD_AFFINITY3_480_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_481_LEN    8
#define GICD_REGS_GICD_AFFINITY3_481_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_482_LEN    8
#define GICD_REGS_GICD_AFFINITY3_482_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_483_LEN    8
#define GICD_REGS_GICD_AFFINITY3_483_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_484_LEN    8
#define GICD_REGS_GICD_AFFINITY3_484_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_485_LEN    8
#define GICD_REGS_GICD_AFFINITY3_485_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_486_LEN    8
#define GICD_REGS_GICD_AFFINITY3_486_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_487_LEN    8
#define GICD_REGS_GICD_AFFINITY3_487_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_488_LEN    8
#define GICD_REGS_GICD_AFFINITY3_488_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_489_LEN    8
#define GICD_REGS_GICD_AFFINITY3_489_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_490_LEN    8
#define GICD_REGS_GICD_AFFINITY3_490_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_491_LEN    8
#define GICD_REGS_GICD_AFFINITY3_491_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_492_LEN    8
#define GICD_REGS_GICD_AFFINITY3_492_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_493_LEN    8
#define GICD_REGS_GICD_AFFINITY3_493_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_494_LEN    8
#define GICD_REGS_GICD_AFFINITY3_494_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_495_LEN    8
#define GICD_REGS_GICD_AFFINITY3_495_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_496_LEN    8
#define GICD_REGS_GICD_AFFINITY3_496_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_497_LEN    8
#define GICD_REGS_GICD_AFFINITY3_497_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_498_LEN    8
#define GICD_REGS_GICD_AFFINITY3_498_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_499_LEN    8
#define GICD_REGS_GICD_AFFINITY3_499_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_500_LEN    8
#define GICD_REGS_GICD_AFFINITY3_500_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_501_LEN    8
#define GICD_REGS_GICD_AFFINITY3_501_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_502_LEN    8
#define GICD_REGS_GICD_AFFINITY3_502_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_503_LEN    8
#define GICD_REGS_GICD_AFFINITY3_503_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_504_LEN    8
#define GICD_REGS_GICD_AFFINITY3_504_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_505_LEN    8
#define GICD_REGS_GICD_AFFINITY3_505_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_506_LEN    8
#define GICD_REGS_GICD_AFFINITY3_506_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_507_LEN    8
#define GICD_REGS_GICD_AFFINITY3_507_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_508_LEN    8
#define GICD_REGS_GICD_AFFINITY3_508_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_509_LEN    8
#define GICD_REGS_GICD_AFFINITY3_509_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_510_LEN    8
#define GICD_REGS_GICD_AFFINITY3_510_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_511_LEN    8
#define GICD_REGS_GICD_AFFINITY3_511_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_512_LEN    8
#define GICD_REGS_GICD_AFFINITY3_512_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_513_LEN    8
#define GICD_REGS_GICD_AFFINITY3_513_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_514_LEN    8
#define GICD_REGS_GICD_AFFINITY3_514_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_515_LEN    8
#define GICD_REGS_GICD_AFFINITY3_515_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_516_LEN    8
#define GICD_REGS_GICD_AFFINITY3_516_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_517_LEN    8
#define GICD_REGS_GICD_AFFINITY3_517_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_518_LEN    8
#define GICD_REGS_GICD_AFFINITY3_518_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_519_LEN    8
#define GICD_REGS_GICD_AFFINITY3_519_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_520_LEN    8
#define GICD_REGS_GICD_AFFINITY3_520_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_521_LEN    8
#define GICD_REGS_GICD_AFFINITY3_521_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_522_LEN    8
#define GICD_REGS_GICD_AFFINITY3_522_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_523_LEN    8
#define GICD_REGS_GICD_AFFINITY3_523_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_524_LEN    8
#define GICD_REGS_GICD_AFFINITY3_524_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_525_LEN    8
#define GICD_REGS_GICD_AFFINITY3_525_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_526_LEN    8
#define GICD_REGS_GICD_AFFINITY3_526_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_527_LEN    8
#define GICD_REGS_GICD_AFFINITY3_527_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_528_LEN    8
#define GICD_REGS_GICD_AFFINITY3_528_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_529_LEN    8
#define GICD_REGS_GICD_AFFINITY3_529_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_530_LEN    8
#define GICD_REGS_GICD_AFFINITY3_530_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_531_LEN    8
#define GICD_REGS_GICD_AFFINITY3_531_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_532_LEN    8
#define GICD_REGS_GICD_AFFINITY3_532_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_533_LEN    8
#define GICD_REGS_GICD_AFFINITY3_533_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_534_LEN    8
#define GICD_REGS_GICD_AFFINITY3_534_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_535_LEN    8
#define GICD_REGS_GICD_AFFINITY3_535_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_536_LEN    8
#define GICD_REGS_GICD_AFFINITY3_536_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_537_LEN    8
#define GICD_REGS_GICD_AFFINITY3_537_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_538_LEN    8
#define GICD_REGS_GICD_AFFINITY3_538_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_539_LEN    8
#define GICD_REGS_GICD_AFFINITY3_539_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_540_LEN    8
#define GICD_REGS_GICD_AFFINITY3_540_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_541_LEN    8
#define GICD_REGS_GICD_AFFINITY3_541_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_542_LEN    8
#define GICD_REGS_GICD_AFFINITY3_542_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_543_LEN    8
#define GICD_REGS_GICD_AFFINITY3_543_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_544_LEN    8
#define GICD_REGS_GICD_AFFINITY3_544_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_545_LEN    8
#define GICD_REGS_GICD_AFFINITY3_545_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_546_LEN    8
#define GICD_REGS_GICD_AFFINITY3_546_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_547_LEN    8
#define GICD_REGS_GICD_AFFINITY3_547_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_548_LEN    8
#define GICD_REGS_GICD_AFFINITY3_548_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_549_LEN    8
#define GICD_REGS_GICD_AFFINITY3_549_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_550_LEN    8
#define GICD_REGS_GICD_AFFINITY3_550_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_551_LEN    8
#define GICD_REGS_GICD_AFFINITY3_551_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_552_LEN    8
#define GICD_REGS_GICD_AFFINITY3_552_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_553_LEN    8
#define GICD_REGS_GICD_AFFINITY3_553_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_554_LEN    8
#define GICD_REGS_GICD_AFFINITY3_554_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_555_LEN    8
#define GICD_REGS_GICD_AFFINITY3_555_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_556_LEN    8
#define GICD_REGS_GICD_AFFINITY3_556_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_557_LEN    8
#define GICD_REGS_GICD_AFFINITY3_557_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_558_LEN    8
#define GICD_REGS_GICD_AFFINITY3_558_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_559_LEN    8
#define GICD_REGS_GICD_AFFINITY3_559_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_560_LEN    8
#define GICD_REGS_GICD_AFFINITY3_560_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_561_LEN    8
#define GICD_REGS_GICD_AFFINITY3_561_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_562_LEN    8
#define GICD_REGS_GICD_AFFINITY3_562_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_563_LEN    8
#define GICD_REGS_GICD_AFFINITY3_563_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_564_LEN    8
#define GICD_REGS_GICD_AFFINITY3_564_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_565_LEN    8
#define GICD_REGS_GICD_AFFINITY3_565_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_566_LEN    8
#define GICD_REGS_GICD_AFFINITY3_566_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_567_LEN    8
#define GICD_REGS_GICD_AFFINITY3_567_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_568_LEN    8
#define GICD_REGS_GICD_AFFINITY3_568_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_569_LEN    8
#define GICD_REGS_GICD_AFFINITY3_569_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_570_LEN    8
#define GICD_REGS_GICD_AFFINITY3_570_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_571_LEN    8
#define GICD_REGS_GICD_AFFINITY3_571_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_572_LEN    8
#define GICD_REGS_GICD_AFFINITY3_572_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_573_LEN    8
#define GICD_REGS_GICD_AFFINITY3_573_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_574_LEN    8
#define GICD_REGS_GICD_AFFINITY3_574_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_575_LEN    8
#define GICD_REGS_GICD_AFFINITY3_575_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_576_LEN    8
#define GICD_REGS_GICD_AFFINITY3_576_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_577_LEN    8
#define GICD_REGS_GICD_AFFINITY3_577_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_578_LEN    8
#define GICD_REGS_GICD_AFFINITY3_578_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_579_LEN    8
#define GICD_REGS_GICD_AFFINITY3_579_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_580_LEN    8
#define GICD_REGS_GICD_AFFINITY3_580_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_581_LEN    8
#define GICD_REGS_GICD_AFFINITY3_581_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_582_LEN    8
#define GICD_REGS_GICD_AFFINITY3_582_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_583_LEN    8
#define GICD_REGS_GICD_AFFINITY3_583_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_584_LEN    8
#define GICD_REGS_GICD_AFFINITY3_584_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_585_LEN    8
#define GICD_REGS_GICD_AFFINITY3_585_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_586_LEN    8
#define GICD_REGS_GICD_AFFINITY3_586_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_587_LEN    8
#define GICD_REGS_GICD_AFFINITY3_587_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_588_LEN    8
#define GICD_REGS_GICD_AFFINITY3_588_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_589_LEN    8
#define GICD_REGS_GICD_AFFINITY3_589_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_590_LEN    8
#define GICD_REGS_GICD_AFFINITY3_590_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_591_LEN    8
#define GICD_REGS_GICD_AFFINITY3_591_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_592_LEN    8
#define GICD_REGS_GICD_AFFINITY3_592_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_593_LEN    8
#define GICD_REGS_GICD_AFFINITY3_593_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_594_LEN    8
#define GICD_REGS_GICD_AFFINITY3_594_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_595_LEN    8
#define GICD_REGS_GICD_AFFINITY3_595_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_596_LEN    8
#define GICD_REGS_GICD_AFFINITY3_596_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_597_LEN    8
#define GICD_REGS_GICD_AFFINITY3_597_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_598_LEN    8
#define GICD_REGS_GICD_AFFINITY3_598_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_599_LEN    8
#define GICD_REGS_GICD_AFFINITY3_599_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_600_LEN    8
#define GICD_REGS_GICD_AFFINITY3_600_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_601_LEN    8
#define GICD_REGS_GICD_AFFINITY3_601_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_602_LEN    8
#define GICD_REGS_GICD_AFFINITY3_602_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_603_LEN    8
#define GICD_REGS_GICD_AFFINITY3_603_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_604_LEN    8
#define GICD_REGS_GICD_AFFINITY3_604_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_605_LEN    8
#define GICD_REGS_GICD_AFFINITY3_605_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_606_LEN    8
#define GICD_REGS_GICD_AFFINITY3_606_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_607_LEN    8
#define GICD_REGS_GICD_AFFINITY3_607_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_608_LEN    8
#define GICD_REGS_GICD_AFFINITY3_608_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_609_LEN    8
#define GICD_REGS_GICD_AFFINITY3_609_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_610_LEN    8
#define GICD_REGS_GICD_AFFINITY3_610_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_611_LEN    8
#define GICD_REGS_GICD_AFFINITY3_611_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_612_LEN    8
#define GICD_REGS_GICD_AFFINITY3_612_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_613_LEN    8
#define GICD_REGS_GICD_AFFINITY3_613_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_614_LEN    8
#define GICD_REGS_GICD_AFFINITY3_614_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_615_LEN    8
#define GICD_REGS_GICD_AFFINITY3_615_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_616_LEN    8
#define GICD_REGS_GICD_AFFINITY3_616_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_617_LEN    8
#define GICD_REGS_GICD_AFFINITY3_617_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_618_LEN    8
#define GICD_REGS_GICD_AFFINITY3_618_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_619_LEN    8
#define GICD_REGS_GICD_AFFINITY3_619_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_620_LEN    8
#define GICD_REGS_GICD_AFFINITY3_620_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_621_LEN    8
#define GICD_REGS_GICD_AFFINITY3_621_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_622_LEN    8
#define GICD_REGS_GICD_AFFINITY3_622_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_623_LEN    8
#define GICD_REGS_GICD_AFFINITY3_623_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_624_LEN    8
#define GICD_REGS_GICD_AFFINITY3_624_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_625_LEN    8
#define GICD_REGS_GICD_AFFINITY3_625_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_626_LEN    8
#define GICD_REGS_GICD_AFFINITY3_626_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_627_LEN    8
#define GICD_REGS_GICD_AFFINITY3_627_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_628_LEN    8
#define GICD_REGS_GICD_AFFINITY3_628_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_629_LEN    8
#define GICD_REGS_GICD_AFFINITY3_629_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_630_LEN    8
#define GICD_REGS_GICD_AFFINITY3_630_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_631_LEN    8
#define GICD_REGS_GICD_AFFINITY3_631_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_632_LEN    8
#define GICD_REGS_GICD_AFFINITY3_632_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_633_LEN    8
#define GICD_REGS_GICD_AFFINITY3_633_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_634_LEN    8
#define GICD_REGS_GICD_AFFINITY3_634_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_635_LEN    8
#define GICD_REGS_GICD_AFFINITY3_635_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_636_LEN    8
#define GICD_REGS_GICD_AFFINITY3_636_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_637_LEN    8
#define GICD_REGS_GICD_AFFINITY3_637_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_638_LEN    8
#define GICD_REGS_GICD_AFFINITY3_638_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_639_LEN    8
#define GICD_REGS_GICD_AFFINITY3_639_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_640_LEN    8
#define GICD_REGS_GICD_AFFINITY3_640_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_641_LEN    8
#define GICD_REGS_GICD_AFFINITY3_641_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_642_LEN    8
#define GICD_REGS_GICD_AFFINITY3_642_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_643_LEN    8
#define GICD_REGS_GICD_AFFINITY3_643_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_644_LEN    8
#define GICD_REGS_GICD_AFFINITY3_644_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_645_LEN    8
#define GICD_REGS_GICD_AFFINITY3_645_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_646_LEN    8
#define GICD_REGS_GICD_AFFINITY3_646_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_647_LEN    8
#define GICD_REGS_GICD_AFFINITY3_647_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_648_LEN    8
#define GICD_REGS_GICD_AFFINITY3_648_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_649_LEN    8
#define GICD_REGS_GICD_AFFINITY3_649_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_650_LEN    8
#define GICD_REGS_GICD_AFFINITY3_650_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_651_LEN    8
#define GICD_REGS_GICD_AFFINITY3_651_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_652_LEN    8
#define GICD_REGS_GICD_AFFINITY3_652_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_653_LEN    8
#define GICD_REGS_GICD_AFFINITY3_653_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_654_LEN    8
#define GICD_REGS_GICD_AFFINITY3_654_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_655_LEN    8
#define GICD_REGS_GICD_AFFINITY3_655_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_656_LEN    8
#define GICD_REGS_GICD_AFFINITY3_656_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_657_LEN    8
#define GICD_REGS_GICD_AFFINITY3_657_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_658_LEN    8
#define GICD_REGS_GICD_AFFINITY3_658_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_659_LEN    8
#define GICD_REGS_GICD_AFFINITY3_659_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_660_LEN    8
#define GICD_REGS_GICD_AFFINITY3_660_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_661_LEN    8
#define GICD_REGS_GICD_AFFINITY3_661_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_662_LEN    8
#define GICD_REGS_GICD_AFFINITY3_662_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_663_LEN    8
#define GICD_REGS_GICD_AFFINITY3_663_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_664_LEN    8
#define GICD_REGS_GICD_AFFINITY3_664_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_665_LEN    8
#define GICD_REGS_GICD_AFFINITY3_665_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_666_LEN    8
#define GICD_REGS_GICD_AFFINITY3_666_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_667_LEN    8
#define GICD_REGS_GICD_AFFINITY3_667_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_668_LEN    8
#define GICD_REGS_GICD_AFFINITY3_668_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_669_LEN    8
#define GICD_REGS_GICD_AFFINITY3_669_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_670_LEN    8
#define GICD_REGS_GICD_AFFINITY3_670_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_671_LEN    8
#define GICD_REGS_GICD_AFFINITY3_671_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_672_LEN    8
#define GICD_REGS_GICD_AFFINITY3_672_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_673_LEN    8
#define GICD_REGS_GICD_AFFINITY3_673_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_674_LEN    8
#define GICD_REGS_GICD_AFFINITY3_674_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_675_LEN    8
#define GICD_REGS_GICD_AFFINITY3_675_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_676_LEN    8
#define GICD_REGS_GICD_AFFINITY3_676_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_677_LEN    8
#define GICD_REGS_GICD_AFFINITY3_677_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_678_LEN    8
#define GICD_REGS_GICD_AFFINITY3_678_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_679_LEN    8
#define GICD_REGS_GICD_AFFINITY3_679_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_680_LEN    8
#define GICD_REGS_GICD_AFFINITY3_680_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_681_LEN    8
#define GICD_REGS_GICD_AFFINITY3_681_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_682_LEN    8
#define GICD_REGS_GICD_AFFINITY3_682_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_683_LEN    8
#define GICD_REGS_GICD_AFFINITY3_683_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_684_LEN    8
#define GICD_REGS_GICD_AFFINITY3_684_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_685_LEN    8
#define GICD_REGS_GICD_AFFINITY3_685_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_686_LEN    8
#define GICD_REGS_GICD_AFFINITY3_686_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_687_LEN    8
#define GICD_REGS_GICD_AFFINITY3_687_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_688_LEN    8
#define GICD_REGS_GICD_AFFINITY3_688_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_689_LEN    8
#define GICD_REGS_GICD_AFFINITY3_689_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_690_LEN    8
#define GICD_REGS_GICD_AFFINITY3_690_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_691_LEN    8
#define GICD_REGS_GICD_AFFINITY3_691_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_692_LEN    8
#define GICD_REGS_GICD_AFFINITY3_692_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_693_LEN    8
#define GICD_REGS_GICD_AFFINITY3_693_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_694_LEN    8
#define GICD_REGS_GICD_AFFINITY3_694_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_695_LEN    8
#define GICD_REGS_GICD_AFFINITY3_695_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_696_LEN    8
#define GICD_REGS_GICD_AFFINITY3_696_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_697_LEN    8
#define GICD_REGS_GICD_AFFINITY3_697_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_698_LEN    8
#define GICD_REGS_GICD_AFFINITY3_698_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_699_LEN    8
#define GICD_REGS_GICD_AFFINITY3_699_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_700_LEN    8
#define GICD_REGS_GICD_AFFINITY3_700_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_701_LEN    8
#define GICD_REGS_GICD_AFFINITY3_701_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_702_LEN    8
#define GICD_REGS_GICD_AFFINITY3_702_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_703_LEN    8
#define GICD_REGS_GICD_AFFINITY3_703_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_704_LEN    8
#define GICD_REGS_GICD_AFFINITY3_704_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_705_LEN    8
#define GICD_REGS_GICD_AFFINITY3_705_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_706_LEN    8
#define GICD_REGS_GICD_AFFINITY3_706_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_707_LEN    8
#define GICD_REGS_GICD_AFFINITY3_707_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_708_LEN    8
#define GICD_REGS_GICD_AFFINITY3_708_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_709_LEN    8
#define GICD_REGS_GICD_AFFINITY3_709_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_710_LEN    8
#define GICD_REGS_GICD_AFFINITY3_710_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_711_LEN    8
#define GICD_REGS_GICD_AFFINITY3_711_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_712_LEN    8
#define GICD_REGS_GICD_AFFINITY3_712_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_713_LEN    8
#define GICD_REGS_GICD_AFFINITY3_713_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_714_LEN    8
#define GICD_REGS_GICD_AFFINITY3_714_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_715_LEN    8
#define GICD_REGS_GICD_AFFINITY3_715_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_716_LEN    8
#define GICD_REGS_GICD_AFFINITY3_716_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_717_LEN    8
#define GICD_REGS_GICD_AFFINITY3_717_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_718_LEN    8
#define GICD_REGS_GICD_AFFINITY3_718_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_719_LEN    8
#define GICD_REGS_GICD_AFFINITY3_719_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_720_LEN    8
#define GICD_REGS_GICD_AFFINITY3_720_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_721_LEN    8
#define GICD_REGS_GICD_AFFINITY3_721_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_722_LEN    8
#define GICD_REGS_GICD_AFFINITY3_722_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_723_LEN    8
#define GICD_REGS_GICD_AFFINITY3_723_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_724_LEN    8
#define GICD_REGS_GICD_AFFINITY3_724_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_725_LEN    8
#define GICD_REGS_GICD_AFFINITY3_725_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_726_LEN    8
#define GICD_REGS_GICD_AFFINITY3_726_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_727_LEN    8
#define GICD_REGS_GICD_AFFINITY3_727_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_728_LEN    8
#define GICD_REGS_GICD_AFFINITY3_728_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_729_LEN    8
#define GICD_REGS_GICD_AFFINITY3_729_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_730_LEN    8
#define GICD_REGS_GICD_AFFINITY3_730_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_731_LEN    8
#define GICD_REGS_GICD_AFFINITY3_731_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_732_LEN    8
#define GICD_REGS_GICD_AFFINITY3_732_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_733_LEN    8
#define GICD_REGS_GICD_AFFINITY3_733_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_734_LEN    8
#define GICD_REGS_GICD_AFFINITY3_734_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_735_LEN    8
#define GICD_REGS_GICD_AFFINITY3_735_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_736_LEN    8
#define GICD_REGS_GICD_AFFINITY3_736_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_737_LEN    8
#define GICD_REGS_GICD_AFFINITY3_737_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_738_LEN    8
#define GICD_REGS_GICD_AFFINITY3_738_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_739_LEN    8
#define GICD_REGS_GICD_AFFINITY3_739_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_740_LEN    8
#define GICD_REGS_GICD_AFFINITY3_740_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_741_LEN    8
#define GICD_REGS_GICD_AFFINITY3_741_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_742_LEN    8
#define GICD_REGS_GICD_AFFINITY3_742_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_743_LEN    8
#define GICD_REGS_GICD_AFFINITY3_743_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_744_LEN    8
#define GICD_REGS_GICD_AFFINITY3_744_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_745_LEN    8
#define GICD_REGS_GICD_AFFINITY3_745_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_746_LEN    8
#define GICD_REGS_GICD_AFFINITY3_746_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_747_LEN    8
#define GICD_REGS_GICD_AFFINITY3_747_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_748_LEN    8
#define GICD_REGS_GICD_AFFINITY3_748_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_749_LEN    8
#define GICD_REGS_GICD_AFFINITY3_749_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_750_LEN    8
#define GICD_REGS_GICD_AFFINITY3_750_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_751_LEN    8
#define GICD_REGS_GICD_AFFINITY3_751_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_752_LEN    8
#define GICD_REGS_GICD_AFFINITY3_752_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_753_LEN    8
#define GICD_REGS_GICD_AFFINITY3_753_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_754_LEN    8
#define GICD_REGS_GICD_AFFINITY3_754_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_755_LEN    8
#define GICD_REGS_GICD_AFFINITY3_755_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_756_LEN    8
#define GICD_REGS_GICD_AFFINITY3_756_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_757_LEN    8
#define GICD_REGS_GICD_AFFINITY3_757_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_758_LEN    8
#define GICD_REGS_GICD_AFFINITY3_758_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_759_LEN    8
#define GICD_REGS_GICD_AFFINITY3_759_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_760_LEN    8
#define GICD_REGS_GICD_AFFINITY3_760_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_761_LEN    8
#define GICD_REGS_GICD_AFFINITY3_761_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_762_LEN    8
#define GICD_REGS_GICD_AFFINITY3_762_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_763_LEN    8
#define GICD_REGS_GICD_AFFINITY3_763_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_764_LEN    8
#define GICD_REGS_GICD_AFFINITY3_764_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_765_LEN    8
#define GICD_REGS_GICD_AFFINITY3_765_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_766_LEN    8
#define GICD_REGS_GICD_AFFINITY3_766_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_767_LEN    8
#define GICD_REGS_GICD_AFFINITY3_767_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_768_LEN    8
#define GICD_REGS_GICD_AFFINITY3_768_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_769_LEN    8
#define GICD_REGS_GICD_AFFINITY3_769_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_770_LEN    8
#define GICD_REGS_GICD_AFFINITY3_770_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_771_LEN    8
#define GICD_REGS_GICD_AFFINITY3_771_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_772_LEN    8
#define GICD_REGS_GICD_AFFINITY3_772_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_773_LEN    8
#define GICD_REGS_GICD_AFFINITY3_773_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_774_LEN    8
#define GICD_REGS_GICD_AFFINITY3_774_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_775_LEN    8
#define GICD_REGS_GICD_AFFINITY3_775_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_776_LEN    8
#define GICD_REGS_GICD_AFFINITY3_776_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_777_LEN    8
#define GICD_REGS_GICD_AFFINITY3_777_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_778_LEN    8
#define GICD_REGS_GICD_AFFINITY3_778_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_779_LEN    8
#define GICD_REGS_GICD_AFFINITY3_779_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_780_LEN    8
#define GICD_REGS_GICD_AFFINITY3_780_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_781_LEN    8
#define GICD_REGS_GICD_AFFINITY3_781_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_782_LEN    8
#define GICD_REGS_GICD_AFFINITY3_782_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_783_LEN    8
#define GICD_REGS_GICD_AFFINITY3_783_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_784_LEN    8
#define GICD_REGS_GICD_AFFINITY3_784_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_785_LEN    8
#define GICD_REGS_GICD_AFFINITY3_785_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_786_LEN    8
#define GICD_REGS_GICD_AFFINITY3_786_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_787_LEN    8
#define GICD_REGS_GICD_AFFINITY3_787_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_788_LEN    8
#define GICD_REGS_GICD_AFFINITY3_788_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_789_LEN    8
#define GICD_REGS_GICD_AFFINITY3_789_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_790_LEN    8
#define GICD_REGS_GICD_AFFINITY3_790_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_791_LEN    8
#define GICD_REGS_GICD_AFFINITY3_791_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_792_LEN    8
#define GICD_REGS_GICD_AFFINITY3_792_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_793_LEN    8
#define GICD_REGS_GICD_AFFINITY3_793_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_794_LEN    8
#define GICD_REGS_GICD_AFFINITY3_794_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_795_LEN    8
#define GICD_REGS_GICD_AFFINITY3_795_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_796_LEN    8
#define GICD_REGS_GICD_AFFINITY3_796_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_797_LEN    8
#define GICD_REGS_GICD_AFFINITY3_797_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_798_LEN    8
#define GICD_REGS_GICD_AFFINITY3_798_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_799_LEN    8
#define GICD_REGS_GICD_AFFINITY3_799_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_800_LEN    8
#define GICD_REGS_GICD_AFFINITY3_800_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_801_LEN    8
#define GICD_REGS_GICD_AFFINITY3_801_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_802_LEN    8
#define GICD_REGS_GICD_AFFINITY3_802_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_803_LEN    8
#define GICD_REGS_GICD_AFFINITY3_803_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_804_LEN    8
#define GICD_REGS_GICD_AFFINITY3_804_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_805_LEN    8
#define GICD_REGS_GICD_AFFINITY3_805_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_806_LEN    8
#define GICD_REGS_GICD_AFFINITY3_806_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_807_LEN    8
#define GICD_REGS_GICD_AFFINITY3_807_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_808_LEN    8
#define GICD_REGS_GICD_AFFINITY3_808_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_809_LEN    8
#define GICD_REGS_GICD_AFFINITY3_809_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_810_LEN    8
#define GICD_REGS_GICD_AFFINITY3_810_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_811_LEN    8
#define GICD_REGS_GICD_AFFINITY3_811_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_812_LEN    8
#define GICD_REGS_GICD_AFFINITY3_812_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_813_LEN    8
#define GICD_REGS_GICD_AFFINITY3_813_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_814_LEN    8
#define GICD_REGS_GICD_AFFINITY3_814_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_815_LEN    8
#define GICD_REGS_GICD_AFFINITY3_815_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_816_LEN    8
#define GICD_REGS_GICD_AFFINITY3_816_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_817_LEN    8
#define GICD_REGS_GICD_AFFINITY3_817_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_818_LEN    8
#define GICD_REGS_GICD_AFFINITY3_818_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_819_LEN    8
#define GICD_REGS_GICD_AFFINITY3_819_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_820_LEN    8
#define GICD_REGS_GICD_AFFINITY3_820_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_821_LEN    8
#define GICD_REGS_GICD_AFFINITY3_821_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_822_LEN    8
#define GICD_REGS_GICD_AFFINITY3_822_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_823_LEN    8
#define GICD_REGS_GICD_AFFINITY3_823_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_824_LEN    8
#define GICD_REGS_GICD_AFFINITY3_824_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_825_LEN    8
#define GICD_REGS_GICD_AFFINITY3_825_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_826_LEN    8
#define GICD_REGS_GICD_AFFINITY3_826_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_827_LEN    8
#define GICD_REGS_GICD_AFFINITY3_827_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_828_LEN    8
#define GICD_REGS_GICD_AFFINITY3_828_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_829_LEN    8
#define GICD_REGS_GICD_AFFINITY3_829_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_830_LEN    8
#define GICD_REGS_GICD_AFFINITY3_830_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_831_LEN    8
#define GICD_REGS_GICD_AFFINITY3_831_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_832_LEN    8
#define GICD_REGS_GICD_AFFINITY3_832_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_833_LEN    8
#define GICD_REGS_GICD_AFFINITY3_833_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_834_LEN    8
#define GICD_REGS_GICD_AFFINITY3_834_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_835_LEN    8
#define GICD_REGS_GICD_AFFINITY3_835_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_836_LEN    8
#define GICD_REGS_GICD_AFFINITY3_836_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_837_LEN    8
#define GICD_REGS_GICD_AFFINITY3_837_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_838_LEN    8
#define GICD_REGS_GICD_AFFINITY3_838_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_839_LEN    8
#define GICD_REGS_GICD_AFFINITY3_839_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_840_LEN    8
#define GICD_REGS_GICD_AFFINITY3_840_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_841_LEN    8
#define GICD_REGS_GICD_AFFINITY3_841_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_842_LEN    8
#define GICD_REGS_GICD_AFFINITY3_842_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_843_LEN    8
#define GICD_REGS_GICD_AFFINITY3_843_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_844_LEN    8
#define GICD_REGS_GICD_AFFINITY3_844_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_845_LEN    8
#define GICD_REGS_GICD_AFFINITY3_845_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_846_LEN    8
#define GICD_REGS_GICD_AFFINITY3_846_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_847_LEN    8
#define GICD_REGS_GICD_AFFINITY3_847_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_848_LEN    8
#define GICD_REGS_GICD_AFFINITY3_848_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_849_LEN    8
#define GICD_REGS_GICD_AFFINITY3_849_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_850_LEN    8
#define GICD_REGS_GICD_AFFINITY3_850_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_851_LEN    8
#define GICD_REGS_GICD_AFFINITY3_851_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_852_LEN    8
#define GICD_REGS_GICD_AFFINITY3_852_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_853_LEN    8
#define GICD_REGS_GICD_AFFINITY3_853_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_854_LEN    8
#define GICD_REGS_GICD_AFFINITY3_854_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_855_LEN    8
#define GICD_REGS_GICD_AFFINITY3_855_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_856_LEN    8
#define GICD_REGS_GICD_AFFINITY3_856_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_857_LEN    8
#define GICD_REGS_GICD_AFFINITY3_857_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_858_LEN    8
#define GICD_REGS_GICD_AFFINITY3_858_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_859_LEN    8
#define GICD_REGS_GICD_AFFINITY3_859_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_860_LEN    8
#define GICD_REGS_GICD_AFFINITY3_860_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_861_LEN    8
#define GICD_REGS_GICD_AFFINITY3_861_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_862_LEN    8
#define GICD_REGS_GICD_AFFINITY3_862_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_863_LEN    8
#define GICD_REGS_GICD_AFFINITY3_863_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_864_LEN    8
#define GICD_REGS_GICD_AFFINITY3_864_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_865_LEN    8
#define GICD_REGS_GICD_AFFINITY3_865_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_866_LEN    8
#define GICD_REGS_GICD_AFFINITY3_866_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_867_LEN    8
#define GICD_REGS_GICD_AFFINITY3_867_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_868_LEN    8
#define GICD_REGS_GICD_AFFINITY3_868_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_869_LEN    8
#define GICD_REGS_GICD_AFFINITY3_869_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_870_LEN    8
#define GICD_REGS_GICD_AFFINITY3_870_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_871_LEN    8
#define GICD_REGS_GICD_AFFINITY3_871_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_872_LEN    8
#define GICD_REGS_GICD_AFFINITY3_872_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_873_LEN    8
#define GICD_REGS_GICD_AFFINITY3_873_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_874_LEN    8
#define GICD_REGS_GICD_AFFINITY3_874_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_875_LEN    8
#define GICD_REGS_GICD_AFFINITY3_875_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_876_LEN    8
#define GICD_REGS_GICD_AFFINITY3_876_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_877_LEN    8
#define GICD_REGS_GICD_AFFINITY3_877_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_878_LEN    8
#define GICD_REGS_GICD_AFFINITY3_878_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_879_LEN    8
#define GICD_REGS_GICD_AFFINITY3_879_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_880_LEN    8
#define GICD_REGS_GICD_AFFINITY3_880_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_881_LEN    8
#define GICD_REGS_GICD_AFFINITY3_881_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_882_LEN    8
#define GICD_REGS_GICD_AFFINITY3_882_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_883_LEN    8
#define GICD_REGS_GICD_AFFINITY3_883_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_884_LEN    8
#define GICD_REGS_GICD_AFFINITY3_884_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_885_LEN    8
#define GICD_REGS_GICD_AFFINITY3_885_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_886_LEN    8
#define GICD_REGS_GICD_AFFINITY3_886_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_887_LEN    8
#define GICD_REGS_GICD_AFFINITY3_887_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_888_LEN    8
#define GICD_REGS_GICD_AFFINITY3_888_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_889_LEN    8
#define GICD_REGS_GICD_AFFINITY3_889_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_890_LEN    8
#define GICD_REGS_GICD_AFFINITY3_890_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_891_LEN    8
#define GICD_REGS_GICD_AFFINITY3_891_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_892_LEN    8
#define GICD_REGS_GICD_AFFINITY3_892_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_893_LEN    8
#define GICD_REGS_GICD_AFFINITY3_893_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_894_LEN    8
#define GICD_REGS_GICD_AFFINITY3_894_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_895_LEN    8
#define GICD_REGS_GICD_AFFINITY3_895_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_896_LEN    8
#define GICD_REGS_GICD_AFFINITY3_896_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_897_LEN    8
#define GICD_REGS_GICD_AFFINITY3_897_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_898_LEN    8
#define GICD_REGS_GICD_AFFINITY3_898_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_899_LEN    8
#define GICD_REGS_GICD_AFFINITY3_899_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_900_LEN    8
#define GICD_REGS_GICD_AFFINITY3_900_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_901_LEN    8
#define GICD_REGS_GICD_AFFINITY3_901_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_902_LEN    8
#define GICD_REGS_GICD_AFFINITY3_902_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_903_LEN    8
#define GICD_REGS_GICD_AFFINITY3_903_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_904_LEN    8
#define GICD_REGS_GICD_AFFINITY3_904_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_905_LEN    8
#define GICD_REGS_GICD_AFFINITY3_905_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_906_LEN    8
#define GICD_REGS_GICD_AFFINITY3_906_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_907_LEN    8
#define GICD_REGS_GICD_AFFINITY3_907_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_908_LEN    8
#define GICD_REGS_GICD_AFFINITY3_908_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_909_LEN    8
#define GICD_REGS_GICD_AFFINITY3_909_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_910_LEN    8
#define GICD_REGS_GICD_AFFINITY3_910_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_911_LEN    8
#define GICD_REGS_GICD_AFFINITY3_911_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_912_LEN    8
#define GICD_REGS_GICD_AFFINITY3_912_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_913_LEN    8
#define GICD_REGS_GICD_AFFINITY3_913_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_914_LEN    8
#define GICD_REGS_GICD_AFFINITY3_914_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_915_LEN    8
#define GICD_REGS_GICD_AFFINITY3_915_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_916_LEN    8
#define GICD_REGS_GICD_AFFINITY3_916_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_917_LEN    8
#define GICD_REGS_GICD_AFFINITY3_917_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_918_LEN    8
#define GICD_REGS_GICD_AFFINITY3_918_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_919_LEN    8
#define GICD_REGS_GICD_AFFINITY3_919_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_920_LEN    8
#define GICD_REGS_GICD_AFFINITY3_920_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_921_LEN    8
#define GICD_REGS_GICD_AFFINITY3_921_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_922_LEN    8
#define GICD_REGS_GICD_AFFINITY3_922_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_923_LEN    8
#define GICD_REGS_GICD_AFFINITY3_923_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_924_LEN    8
#define GICD_REGS_GICD_AFFINITY3_924_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_925_LEN    8
#define GICD_REGS_GICD_AFFINITY3_925_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_926_LEN    8
#define GICD_REGS_GICD_AFFINITY3_926_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_927_LEN    8
#define GICD_REGS_GICD_AFFINITY3_927_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_928_LEN    8
#define GICD_REGS_GICD_AFFINITY3_928_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_929_LEN    8
#define GICD_REGS_GICD_AFFINITY3_929_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_930_LEN    8
#define GICD_REGS_GICD_AFFINITY3_930_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_931_LEN    8
#define GICD_REGS_GICD_AFFINITY3_931_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_932_LEN    8
#define GICD_REGS_GICD_AFFINITY3_932_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_933_LEN    8
#define GICD_REGS_GICD_AFFINITY3_933_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_934_LEN    8
#define GICD_REGS_GICD_AFFINITY3_934_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_935_LEN    8
#define GICD_REGS_GICD_AFFINITY3_935_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_936_LEN    8
#define GICD_REGS_GICD_AFFINITY3_936_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_937_LEN    8
#define GICD_REGS_GICD_AFFINITY3_937_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_938_LEN    8
#define GICD_REGS_GICD_AFFINITY3_938_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_939_LEN    8
#define GICD_REGS_GICD_AFFINITY3_939_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_940_LEN    8
#define GICD_REGS_GICD_AFFINITY3_940_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_941_LEN    8
#define GICD_REGS_GICD_AFFINITY3_941_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_942_LEN    8
#define GICD_REGS_GICD_AFFINITY3_942_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_943_LEN    8
#define GICD_REGS_GICD_AFFINITY3_943_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_944_LEN    8
#define GICD_REGS_GICD_AFFINITY3_944_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_945_LEN    8
#define GICD_REGS_GICD_AFFINITY3_945_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_946_LEN    8
#define GICD_REGS_GICD_AFFINITY3_946_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_947_LEN    8
#define GICD_REGS_GICD_AFFINITY3_947_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_948_LEN    8
#define GICD_REGS_GICD_AFFINITY3_948_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_949_LEN    8
#define GICD_REGS_GICD_AFFINITY3_949_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_950_LEN    8
#define GICD_REGS_GICD_AFFINITY3_950_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_951_LEN    8
#define GICD_REGS_GICD_AFFINITY3_951_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_952_LEN    8
#define GICD_REGS_GICD_AFFINITY3_952_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_953_LEN    8
#define GICD_REGS_GICD_AFFINITY3_953_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_954_LEN    8
#define GICD_REGS_GICD_AFFINITY3_954_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_955_LEN    8
#define GICD_REGS_GICD_AFFINITY3_955_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_956_LEN    8
#define GICD_REGS_GICD_AFFINITY3_956_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_957_LEN    8
#define GICD_REGS_GICD_AFFINITY3_957_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_958_LEN    8
#define GICD_REGS_GICD_AFFINITY3_958_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_959_LEN    8
#define GICD_REGS_GICD_AFFINITY3_959_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_960_LEN    8
#define GICD_REGS_GICD_AFFINITY3_960_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_961_LEN    8
#define GICD_REGS_GICD_AFFINITY3_961_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_962_LEN    8
#define GICD_REGS_GICD_AFFINITY3_962_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_963_LEN    8
#define GICD_REGS_GICD_AFFINITY3_963_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_964_LEN    8
#define GICD_REGS_GICD_AFFINITY3_964_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_965_LEN    8
#define GICD_REGS_GICD_AFFINITY3_965_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_966_LEN    8
#define GICD_REGS_GICD_AFFINITY3_966_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_967_LEN    8
#define GICD_REGS_GICD_AFFINITY3_967_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_968_LEN    8
#define GICD_REGS_GICD_AFFINITY3_968_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_969_LEN    8
#define GICD_REGS_GICD_AFFINITY3_969_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_970_LEN    8
#define GICD_REGS_GICD_AFFINITY3_970_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_971_LEN    8
#define GICD_REGS_GICD_AFFINITY3_971_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_972_LEN    8
#define GICD_REGS_GICD_AFFINITY3_972_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_973_LEN    8
#define GICD_REGS_GICD_AFFINITY3_973_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_974_LEN    8
#define GICD_REGS_GICD_AFFINITY3_974_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_975_LEN    8
#define GICD_REGS_GICD_AFFINITY3_975_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_976_LEN    8
#define GICD_REGS_GICD_AFFINITY3_976_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_977_LEN    8
#define GICD_REGS_GICD_AFFINITY3_977_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_978_LEN    8
#define GICD_REGS_GICD_AFFINITY3_978_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_979_LEN    8
#define GICD_REGS_GICD_AFFINITY3_979_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_980_LEN    8
#define GICD_REGS_GICD_AFFINITY3_980_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_981_LEN    8
#define GICD_REGS_GICD_AFFINITY3_981_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_982_LEN    8
#define GICD_REGS_GICD_AFFINITY3_982_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_983_LEN    8
#define GICD_REGS_GICD_AFFINITY3_983_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_984_LEN    8
#define GICD_REGS_GICD_AFFINITY3_984_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_985_LEN    8
#define GICD_REGS_GICD_AFFINITY3_985_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_986_LEN    8
#define GICD_REGS_GICD_AFFINITY3_986_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_987_LEN    8
#define GICD_REGS_GICD_AFFINITY3_987_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_988_LEN    8
#define GICD_REGS_GICD_AFFINITY3_988_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_989_LEN    8
#define GICD_REGS_GICD_AFFINITY3_989_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_990_LEN    8
#define GICD_REGS_GICD_AFFINITY3_990_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_991_LEN    8
#define GICD_REGS_GICD_AFFINITY3_991_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_992_LEN    8
#define GICD_REGS_GICD_AFFINITY3_992_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_993_LEN    8
#define GICD_REGS_GICD_AFFINITY3_993_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_994_LEN    8
#define GICD_REGS_GICD_AFFINITY3_994_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_995_LEN    8
#define GICD_REGS_GICD_AFFINITY3_995_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_996_LEN    8
#define GICD_REGS_GICD_AFFINITY3_996_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_997_LEN    8
#define GICD_REGS_GICD_AFFINITY3_997_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_998_LEN    8
#define GICD_REGS_GICD_AFFINITY3_998_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_999_LEN    8
#define GICD_REGS_GICD_AFFINITY3_999_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1000_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1000_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1001_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1001_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1002_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1002_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1003_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1003_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1004_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1004_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1005_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1005_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1006_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1006_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1007_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1007_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1008_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1008_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1009_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1009_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1010_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1010_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1011_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1011_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1012_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1012_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1013_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1013_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1014_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1014_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1015_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1015_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1016_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1016_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1017_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1017_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1018_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1018_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1019_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1019_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1020_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1020_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1021_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1021_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1022_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1022_OFFSET 0

#define GICD_REGS_GICD_AFFINITY3_1023_LEN    8
#define GICD_REGS_GICD_AFFINITY3_1023_OFFSET 0

#define GICD_REGS_COMPONENT_ID0_LEN    8
#define GICD_REGS_COMPONENT_ID0_OFFSET 0

#define GICD_REGS_COMPONENT_ID1_LEN    8
#define GICD_REGS_COMPONENT_ID1_OFFSET 0

#define GICD_REGS_COMPONENT_ID2_LEN    8
#define GICD_REGS_COMPONENT_ID2_OFFSET 0

#define GICD_REGS_COMPONENT_ID3_LEN    8
#define GICD_REGS_COMPONENT_ID3_OFFSET 0

#define GICD_REGS_CONTINUEID_LEN    4
#define GICD_REGS_CONTINUEID_OFFSET 0







#define GICD_REGS_DEVID__L_LEN    8
#define GICD_REGS_DEVID__L_OFFSET 0

#define GICD_REGS_JEDECID_L_LEN    4
#define GICD_REGS_JEDECID_L_OFFSET 4
#define GICD_REGS_DEVID_H_LEN      4
#define GICD_REGS_DEVID_H_OFFSET   0

#define GICD_REGS_ARCHREV_LEN       4
#define GICD_REGS_ARCHREV_OFFSET    4
#define GICD_REGS_JEDECID_EN_LEN    1
#define GICD_REGS_JEDECID_EN_OFFSET 3
#define GICD_REGS_JEDECID_H_LEN     3
#define GICD_REGS_JEDECID_H_OFFSET  0



#define GICD_REGS_INT_TIMEOUT_ENABLE_LEN    1
#define GICD_REGS_INT_TIMEOUT_ENABLE_OFFSET 31
#define GICD_REGS_INT_TIMEOUT_SET_LEN       20
#define GICD_REGS_INT_TIMEOUT_SET_OFFSET    10

#define GICD_REGS_VERSION_ID_LEN    32
#define GICD_REGS_VERSION_ID_OFFSET 0

#define GICD_REGS_PCIE_INTX_SET_LEN    10
#define GICD_REGS_PCIE_INTX_SET_OFFSET 0

#define GICD_REGS_PCIE_INTX_CLR_LEN    10
#define GICD_REGS_PCIE_INTX_CLR_OFFSET 0

#define GICD_REGS_GICD_FUNC_EN_LEN    16
#define GICD_REGS_GICD_FUNC_EN_OFFSET 0

#define GICD_REGS_SPIS_CROSS_SET_CROSSCLR_STS_EN_LEN    1
#define GICD_REGS_SPIS_CROSS_SET_CROSSCLR_STS_EN_OFFSET 0

#define GICD_REGS_GICD_TARGETLIST_0_LEN    16
#define GICD_REGS_GICD_TARGETLIST_0_OFFSET 0

#define GICD_REGS_GICD_FILTER_LEN          2
#define GICD_REGS_GICD_FILTER_OFFSET       24
#define GICD_REGS_GICD_TARGETLIST_1_LEN    16
#define GICD_REGS_GICD_TARGETLIST_1_OFFSET 8
#define GICD_REGS_NSATT_LEN                1
#define GICD_REGS_NSATT_OFFSET             7
#define GICD_REGS_GICD_SGT_LEN             2
#define GICD_REGS_GICD_SGT_OFFSET          5
#define GICD_REGS_GICD_NS_LEN              1
#define GICD_REGS_GICD_NS_OFFSET           4
#define GICD_REGS_GICD_SGIID_LEN           4
#define GICD_REGS_GICD_SGIID_OFFSET        0

#define GICD_REGS_DFX_CPU_SEL_LEN         5
#define GICD_REGS_DFX_CPU_SEL_OFFSET      24
#define GICD_REGS_DFX_MON_LPI_CMD_LEN     4
#define GICD_REGS_DFX_MON_LPI_CMD_OFFSET  20
#define GICD_REGS_DFX_INT_TYPE_SEL_LEN    1
#define GICD_REGS_DFX_INT_TYPE_SEL_OFFSET 16
#define GICD_REGS_DFX_MON_ID_LEN          16
#define GICD_REGS_DFX_MON_ID_OFFSET       0

#define GICD_REGS_SNAP_EN_LEN       1
#define GICD_REGS_SNAP_EN_OFFSET    1
#define GICD_REGS_CNT_CLR_CE_LEN    1
#define GICD_REGS_CNT_CLR_CE_OFFSET 0

#define GICD_REGS_DFX_CPUIF_INT_ACP_LEN    32
#define GICD_REGS_DFX_CPUIF_INT_ACP_OFFSET 0

#define GICD_REGS_DFX_CPUIF_LEGACY_RDY_LEN    16
#define GICD_REGS_DFX_CPUIF_LEGACY_RDY_OFFSET 0

#define GICD_REGS_DFX_CPUIF_LEGACY_ACTIVE_LEN    16
#define GICD_REGS_DFX_CPUIF_LEGACY_ACTIVE_OFFSET 0

#define GICD_REGS_DFX_CPUIF_LEGACY_DEACTIVATE_LEN    16
#define GICD_REGS_DFX_CPUIF_LEGACY_DEACTIVATE_OFFSET 0

#define GICD_REGS_DFX_CPUIF_LPI_RDY_LEN    16
#define GICD_REGS_DFX_CPUIF_LPI_RDY_OFFSET 0

#define GICD_REGS_DFX_CPUIF_LPI_ACK_LEN    16
#define GICD_REGS_DFX_CPUIF_LPI_ACK_OFFSET 0

#define GICD_REGS_DFX_CPUIF_VLPI_RDY_LEN    16
#define GICD_REGS_DFX_CPUIF_VLPI_RDY_OFFSET 0

#define GICD_REGS_DFX_CPUIF_VLPI_ACK_LEN    16
#define GICD_REGS_DFX_CPUIF_VLPI_ACK_OFFSET 0

#define GICD_REGS_DFX_SPI_GRP_SEL_LEN    5
#define GICD_REGS_DFX_SPI_GRP_SEL_OFFSET 0

#define GICD_REGS_DFX_SPIS_EOI_ERR_LEN      1
#define GICD_REGS_DFX_SPIS_EOI_ERR_OFFSET   3
#define GICD_REGS_DFX_LOWIDS_EOI_ERR_LEN    1
#define GICD_REGS_DFX_LOWIDS_EOI_ERR_OFFSET 2
#define GICD_REGS_DFX_GICD_CFG_ERR_LEN      2
#define GICD_REGS_DFX_GICD_CFG_ERR_OFFSET   0

#define GICD_REGS_DFX_LOWIDS_MERGE_LEN    32
#define GICD_REGS_DFX_LOWIDS_MERGE_OFFSET 0

#define GICD_REGS_DFX_LOWIDS_SPLIT_LEN    32
#define GICD_REGS_DFX_LOWIDS_SPLIT_OFFSET 0

#define GICD_REGS_DFX_LOWIDS_DROP_LEN    32
#define GICD_REGS_DFX_LOWIDS_DROP_OFFSET 0

#define GICD_REGS_DFX_SPIS_MERGE_LEN    32
#define GICD_REGS_DFX_SPIS_MERGE_OFFSET 0

#define GICD_REGS_DFX_SPIS_SPLIT_LEN    32
#define GICD_REGS_DFX_SPIS_SPLIT_OFFSET 0

#define GICD_REGS_DFX_SPIS_DROP_LEN    32
#define GICD_REGS_DFX_SPIS_DROP_OFFSET 0

#define GICD_REGS_DFX_ID_SET_MAX_LEN        16
#define GICD_REGS_DFX_ID_SET_MAX_OFFSET     16
#define GICD_REGS_DFX_ID_SET_MAXTIME_LEN    16
#define GICD_REGS_DFX_ID_SET_MAXTIME_OFFSET 0

#define GICD_REGS_DFX_ID_EOI_MAX_LEN    16
#define GICD_REGS_DFX_ID_EOI_MAX_OFFSET 0



#define GICD_REGS_GICV2M_ARC_REV_LEN    4
#define GICD_REGS_GICV2M_ARC_REV_OFFSET 4

#define GICD_REGS_BASE_SPI_NUMBER_LEN    10
#define GICD_REGS_BASE_SPI_NUMBER_OFFSET 16
#define GICD_REGS_NUMBER_SPIS_LEN        10
#define GICD_REGS_NUMBER_SPIS_OFFSET     0

#define GICD_REGS_MSI_SETSPI_NS_LEN    10
#define GICD_REGS_MSI_SETSPI_NS_OFFSET 0

#define GICD_REGS_GICV2M_PRODUCTID_LEN       8
#define GICD_REGS_GICV2M_PRODUCTID_OFFSET    24
#define GICD_REGS_GICV2M_ARC_REV_LEN         4
#define GICD_REGS_GICV2M_ARC_REV_OFFSET      16
#define GICD_REGS_GICV2M_MSI_REVISION_LEN    4
#define GICD_REGS_GICV2M_MSI_REVISION_OFFSET 12
#define GICD_REGS_GICV2M_IMPLEMENTER_LEN     12
#define GICD_REGS_GICV2M_IMPLEMENTER_OFFSET  0

#define GICD_REGS_BASE_SPI_NUMBER_LEN    10
#define GICD_REGS_BASE_SPI_NUMBER_OFFSET 16
#define GICD_REGS_NUMBER_SPIS_LEN        10
#define GICD_REGS_NUMBER_SPIS_OFFSET     0

#define GICD_REGS_MSI_SETSPI_S_LEN    10
#define GICD_REGS_MSI_SETSPI_S_OFFSET 0

#define GICD_REGS_GICV2M_PRODUCTID_LEN       8
#define GICD_REGS_GICV2M_PRODUCTID_OFFSET    24
#define GICD_REGS_GICV2M_ARC_REV_LEN         4
#define GICD_REGS_GICV2M_ARC_REV_OFFSET      16
#define GICD_REGS_GICV2M_MSI_REVISION_LEN    4
#define GICD_REGS_GICV2M_MSI_REVISION_OFFSET 12
#define GICD_REGS_GICV2M_IMPLEMENTER_LEN     12
#define GICD_REGS_GICV2M_IMPLEMENTER_OFFSET  0

#define GICD_REGS_DFX_NODE_INFO_LEN    32
#define GICD_REGS_DFX_NODE_INFO_OFFSET 0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_0_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_0_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_0_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_0_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_0_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_0_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_0_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_0_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_0_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_0_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_1_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_1_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_1_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_1_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_1_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_1_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_1_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_1_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_1_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_1_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_2_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_2_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_2_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_2_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_2_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_2_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_2_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_2_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_2_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_2_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_3_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_3_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_3_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_3_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_3_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_3_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_3_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_3_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_3_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_3_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_4_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_4_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_4_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_4_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_4_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_4_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_4_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_4_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_4_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_4_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_5_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_5_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_5_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_5_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_5_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_5_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_5_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_5_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_5_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_5_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_6_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_6_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_6_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_6_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_6_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_6_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_6_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_6_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_6_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_6_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_7_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_7_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_7_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_7_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_7_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_7_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_7_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_7_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_7_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_7_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_8_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_8_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_8_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_8_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_8_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_8_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_8_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_8_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_8_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_8_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_9_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_9_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_9_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_9_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_9_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_9_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_9_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_9_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_9_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_9_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_10_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_10_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_10_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_10_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_10_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_10_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_10_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_10_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_10_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_10_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_11_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_11_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_11_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_11_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_11_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_11_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_11_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_11_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_11_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_11_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_12_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_12_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_12_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_12_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_12_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_12_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_12_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_12_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_12_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_12_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_13_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_13_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_13_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_13_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_13_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_13_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_13_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_13_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_13_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_13_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_14_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_14_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_14_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_14_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_14_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_14_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_14_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_14_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_14_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_14_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_15_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_15_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_15_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_15_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_15_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_15_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_15_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_15_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_15_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_15_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_16_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_16_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_16_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_16_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_16_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_16_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_16_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_16_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_16_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_16_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_17_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_17_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_17_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_17_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_17_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_17_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_17_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_17_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_17_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_17_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_18_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_18_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_18_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_18_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_18_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_18_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_18_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_18_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_18_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_18_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_19_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_19_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_19_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_19_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_19_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_19_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_19_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_19_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_19_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_19_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_20_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_20_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_20_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_20_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_20_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_20_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_20_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_20_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_20_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_20_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_21_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_21_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_21_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_21_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_21_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_21_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_21_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_21_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_21_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_21_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_22_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_22_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_22_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_22_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_22_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_22_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_22_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_22_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_22_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_22_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_23_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_23_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_23_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_23_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_23_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_23_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_23_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_23_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_23_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_23_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_24_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_24_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_24_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_24_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_24_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_24_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_24_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_24_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_24_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_24_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_25_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_25_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_25_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_25_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_25_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_25_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_25_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_25_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_25_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_25_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_26_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_26_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_26_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_26_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_26_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_26_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_26_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_26_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_26_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_26_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_27_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_27_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_27_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_27_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_27_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_27_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_27_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_27_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_27_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_27_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_28_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_28_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_28_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_28_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_28_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_28_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_28_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_28_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_28_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_28_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_29_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_29_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_29_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_29_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_29_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_29_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_29_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_29_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_29_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_29_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_30_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_30_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_30_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_30_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_30_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_30_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_30_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_30_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_30_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_30_OFFSET    0

#define GICD_REGS_DFX_ICDT_FSM_IDLE_31_LEN        1
#define GICD_REGS_DFX_ICDT_FSM_IDLE_31_OFFSET     31
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_31_LEN      2
#define GICD_REGS_DFX_ICDT_CHL_GRPMOD_31_OFFSET   29
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_31_LEN    5
#define GICD_REGS_DFX_ICDT_CHL_SRCCPUID_31_OFFSET 24
#define GICD_REGS_DFX_ICDT_CHL_PRI_31_LEN         8
#define GICD_REGS_DFX_ICDT_CHL_PRI_31_OFFSET      16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_31_LEN       16
#define GICD_REGS_DFX_ICDT_CHL_IRQID_31_OFFSET    0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_0_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_0_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_0_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_0_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_0_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_0_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_0_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_0_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_0_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_0_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_0_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_0_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_0_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_0_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_1_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_1_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_1_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_1_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_1_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_1_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_1_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_1_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_1_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_1_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_1_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_1_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_1_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_1_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_2_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_2_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_2_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_2_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_2_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_2_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_2_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_2_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_2_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_2_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_2_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_2_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_2_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_2_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_3_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_3_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_3_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_3_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_3_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_3_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_3_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_3_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_3_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_3_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_3_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_3_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_3_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_3_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_4_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_4_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_4_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_4_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_4_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_4_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_4_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_4_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_4_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_4_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_4_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_4_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_4_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_4_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_5_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_5_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_5_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_5_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_5_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_5_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_5_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_5_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_5_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_5_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_5_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_5_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_5_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_5_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_6_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_6_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_6_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_6_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_6_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_6_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_6_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_6_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_6_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_6_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_6_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_6_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_6_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_6_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_7_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_7_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_7_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_7_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_7_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_7_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_7_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_7_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_7_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_7_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_7_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_7_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_7_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_7_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_8_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_8_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_8_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_8_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_8_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_8_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_8_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_8_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_8_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_8_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_8_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_8_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_8_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_8_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_9_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_9_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_9_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_9_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_9_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_9_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_9_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_9_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_9_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_9_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_9_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_9_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_9_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_9_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_10_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_10_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_10_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_10_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_10_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_10_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_10_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_10_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_10_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_10_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_10_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_10_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_10_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_10_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_11_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_11_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_11_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_11_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_11_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_11_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_11_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_11_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_11_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_11_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_11_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_11_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_11_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_11_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_12_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_12_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_12_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_12_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_12_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_12_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_12_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_12_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_12_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_12_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_12_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_12_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_12_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_12_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_13_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_13_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_13_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_13_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_13_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_13_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_13_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_13_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_13_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_13_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_13_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_13_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_13_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_13_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_14_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_14_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_14_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_14_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_14_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_14_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_14_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_14_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_14_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_14_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_14_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_14_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_14_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_14_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_15_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_15_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_15_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_15_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_15_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_15_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_15_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_15_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_15_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_15_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_15_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_15_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_15_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_15_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_16_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_16_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_16_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_16_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_16_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_16_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_16_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_16_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_16_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_16_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_16_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_16_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_16_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_16_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_17_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_17_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_17_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_17_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_17_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_17_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_17_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_17_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_17_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_17_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_17_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_17_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_17_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_17_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_18_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_18_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_18_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_18_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_18_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_18_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_18_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_18_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_18_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_18_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_18_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_18_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_18_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_18_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_19_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_19_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_19_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_19_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_19_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_19_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_19_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_19_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_19_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_19_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_19_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_19_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_19_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_19_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_20_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_20_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_20_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_20_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_20_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_20_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_20_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_20_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_20_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_20_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_20_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_20_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_20_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_20_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_21_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_21_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_21_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_21_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_21_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_21_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_21_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_21_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_21_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_21_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_21_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_21_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_21_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_21_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_22_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_22_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_22_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_22_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_22_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_22_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_22_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_22_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_22_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_22_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_22_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_22_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_22_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_22_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_23_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_23_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_23_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_23_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_23_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_23_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_23_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_23_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_23_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_23_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_23_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_23_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_23_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_23_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_24_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_24_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_24_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_24_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_24_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_24_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_24_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_24_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_24_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_24_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_24_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_24_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_24_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_24_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_25_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_25_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_25_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_25_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_25_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_25_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_25_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_25_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_25_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_25_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_25_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_25_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_25_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_25_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_26_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_26_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_26_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_26_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_26_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_26_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_26_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_26_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_26_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_26_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_26_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_26_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_26_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_26_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_27_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_27_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_27_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_27_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_27_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_27_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_27_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_27_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_27_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_27_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_27_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_27_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_27_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_27_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_28_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_28_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_28_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_28_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_28_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_28_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_28_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_28_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_28_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_28_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_28_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_28_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_28_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_28_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_29_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_29_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_29_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_29_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_29_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_29_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_29_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_29_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_29_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_29_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_29_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_29_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_29_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_29_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_30_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_30_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_30_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_30_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_30_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_30_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_30_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_30_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_30_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_30_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_30_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_30_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_30_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_30_OFFSET          0

#define GICD_REGS_DFX_IRQSET_TOUTCNT_31_LEN         4
#define GICD_REGS_DFX_IRQSET_TOUTCNT_31_OFFSET      28
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_31_LEN    1
#define GICD_REGS_DFX_ICCT_PKT_RELEASEERR_31_OFFSET 23
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_31_LEN     1
#define GICD_REGS_DFX_ICCT_PKT_ACTIVEERR_31_OFFSET  22
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_31_LEN        1
#define GICD_REGS_DFX_ICCT_PKT_CLRERR_31_OFFSET     21
#define GICD_REGS_DFX_ICDT_CHL_VCMD_31_LEN          1
#define GICD_REGS_DFX_ICDT_CHL_VCMD_31_OFFSET       20
#define GICD_REGS_DFX_ICDTCMD_PENDING_31_LEN        16
#define GICD_REGS_DFX_ICDTCMD_PENDING_31_OFFSET     4
#define GICD_REGS_DFX_IRQSET_FSM_31_LEN             4
#define GICD_REGS_DFX_IRQSET_FSM_31_OFFSET          0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_0_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_0_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_1_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_1_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_2_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_2_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_3_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_3_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_4_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_4_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_5_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_5_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_6_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_6_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_7_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_7_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_8_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_8_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_9_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_9_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_10_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_10_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_11_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_11_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_12_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_12_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_13_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_13_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_14_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_14_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_15_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_15_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_16_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_16_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_17_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_17_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_18_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_18_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_19_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_19_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_20_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_20_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_21_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_21_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_22_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_22_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_23_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_23_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_24_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_24_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_25_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_25_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_26_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_26_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_27_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_27_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_28_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_28_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_29_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_29_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_30_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_30_OFFSET 0

#define GICD_REGS_DFX_ICCT_PKT_GENSGI_31_LEN    24
#define GICD_REGS_DFX_ICCT_PKT_GENSGI_31_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_0_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_0_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_0_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_0_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_0_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_0_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_0_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_0_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_0_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_0_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_0_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_0_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_0_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_0_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_1_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_1_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_1_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_1_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_1_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_1_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_1_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_1_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_1_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_1_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_1_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_1_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_1_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_1_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_2_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_2_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_2_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_2_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_2_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_2_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_2_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_2_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_2_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_2_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_2_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_2_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_2_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_2_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_3_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_3_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_3_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_3_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_3_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_3_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_3_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_3_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_3_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_3_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_3_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_3_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_3_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_3_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_4_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_4_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_4_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_4_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_4_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_4_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_4_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_4_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_4_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_4_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_4_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_4_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_4_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_4_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_5_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_5_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_5_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_5_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_5_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_5_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_5_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_5_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_5_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_5_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_5_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_5_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_5_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_5_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_6_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_6_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_6_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_6_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_6_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_6_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_6_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_6_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_6_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_6_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_6_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_6_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_6_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_6_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_7_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_7_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_7_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_7_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_7_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_7_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_7_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_7_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_7_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_7_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_7_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_7_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_7_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_7_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_8_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_8_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_8_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_8_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_8_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_8_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_8_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_8_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_8_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_8_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_8_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_8_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_8_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_8_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_9_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_9_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_9_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_9_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_9_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_9_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_9_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_9_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_9_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_9_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_9_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_9_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_9_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_9_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_10_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_10_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_10_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_10_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_10_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_10_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_10_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_10_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_10_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_10_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_10_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_10_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_10_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_10_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_11_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_11_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_11_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_11_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_11_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_11_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_11_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_11_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_11_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_11_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_11_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_11_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_11_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_11_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_12_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_12_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_12_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_12_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_12_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_12_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_12_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_12_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_12_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_12_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_12_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_12_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_12_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_12_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_13_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_13_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_13_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_13_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_13_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_13_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_13_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_13_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_13_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_13_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_13_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_13_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_13_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_13_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_14_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_14_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_14_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_14_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_14_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_14_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_14_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_14_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_14_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_14_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_14_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_14_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_14_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_14_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_15_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_15_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_15_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_15_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_15_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_15_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_15_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_15_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_15_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_15_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_15_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_15_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_15_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_15_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_16_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_16_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_16_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_16_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_16_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_16_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_16_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_16_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_16_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_16_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_16_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_16_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_16_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_16_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_17_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_17_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_17_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_17_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_17_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_17_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_17_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_17_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_17_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_17_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_17_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_17_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_17_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_17_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_18_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_18_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_18_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_18_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_18_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_18_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_18_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_18_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_18_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_18_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_18_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_18_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_18_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_18_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_19_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_19_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_19_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_19_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_19_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_19_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_19_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_19_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_19_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_19_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_19_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_19_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_19_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_19_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_20_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_20_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_20_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_20_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_20_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_20_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_20_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_20_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_20_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_20_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_20_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_20_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_20_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_20_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_21_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_21_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_21_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_21_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_21_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_21_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_21_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_21_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_21_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_21_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_21_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_21_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_21_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_21_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_22_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_22_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_22_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_22_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_22_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_22_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_22_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_22_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_22_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_22_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_22_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_22_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_22_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_22_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_23_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_23_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_23_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_23_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_23_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_23_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_23_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_23_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_23_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_23_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_23_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_23_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_23_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_23_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_24_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_24_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_24_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_24_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_24_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_24_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_24_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_24_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_24_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_24_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_24_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_24_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_24_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_24_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_25_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_25_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_25_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_25_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_25_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_25_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_25_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_25_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_25_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_25_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_25_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_25_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_25_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_25_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_26_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_26_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_26_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_26_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_26_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_26_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_26_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_26_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_26_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_26_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_26_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_26_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_26_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_26_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_27_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_27_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_27_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_27_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_27_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_27_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_27_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_27_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_27_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_27_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_27_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_27_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_27_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_27_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_28_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_28_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_28_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_28_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_28_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_28_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_28_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_28_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_28_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_28_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_28_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_28_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_28_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_28_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_29_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_29_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_29_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_29_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_29_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_29_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_29_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_29_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_29_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_29_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_29_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_29_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_29_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_29_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_30_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_30_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_30_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_30_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_30_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_30_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_30_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_30_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_30_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_30_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_30_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_30_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_30_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_30_OFFSET 0

#define GICD_REGS_DFX_ERR_IRQID_31_LEN                16
#define GICD_REGS_DFX_ERR_IRQID_31_OFFSET             16
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_31_LEN           1
#define GICD_REGS_DFX_CPUIF_HIGH_REQ_31_OFFSET        13
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_31_LEN           1
#define GICD_REGS_DFX_CPUIF_VLPI_REQ_31_OFFSET        12
#define GICD_REGS_DFX_CPUIF_LPI_REQ_31_LEN            1
#define GICD_REGS_DFX_CPUIF_LPI_REQ_31_OFFSET         11
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_31_LEN      1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_FULL_31_OFFSET   10
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_31_LEN     1
#define GICD_REGS_DFX_CPUIF_CMD_FIFO_EMPTY_31_OFFSET  8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_31_LEN    8
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_PMR_31_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_0_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_0_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_0_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_0_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_1_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_1_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_1_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_1_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_2_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_2_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_2_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_2_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_3_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_3_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_3_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_3_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_4_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_4_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_4_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_4_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_5_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_5_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_5_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_5_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_6_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_6_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_6_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_6_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_7_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_7_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_7_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_7_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_8_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_8_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_8_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_8_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_9_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_9_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_9_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_9_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_10_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_10_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_10_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_10_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_11_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_11_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_11_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_11_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_12_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_12_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_12_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_12_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_13_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_13_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_13_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_13_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_14_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_14_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_14_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_14_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_15_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_15_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_15_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_15_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_16_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_16_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_16_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_16_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_17_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_17_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_17_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_17_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_18_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_18_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_18_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_18_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_19_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_19_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_19_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_19_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_20_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_20_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_20_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_20_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_21_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_21_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_21_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_21_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_22_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_22_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_22_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_22_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_23_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_23_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_23_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_23_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_24_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_24_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_24_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_24_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_25_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_25_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_25_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_25_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_26_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_26_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_26_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_26_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_27_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_27_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_27_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_27_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_28_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_28_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_28_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_28_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_29_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_29_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_29_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_29_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_30_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_30_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_30_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_30_OFFSET 0

#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_31_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA1_31_OFFSET 16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_31_LEN    16
#define GICD_REGS_DFX_CPUIF_STREAM_RECV_DATA0_31_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_0_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_0_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_0_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_0_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_1_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_1_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_1_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_1_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_2_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_2_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_2_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_2_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_3_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_3_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_3_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_3_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_4_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_4_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_4_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_4_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_5_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_5_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_5_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_5_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_6_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_6_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_6_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_6_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_7_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_7_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_7_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_7_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_8_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_8_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_8_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_8_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_9_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_9_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_9_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_9_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_10_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_10_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_10_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_10_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_11_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_11_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_11_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_11_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_12_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_12_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_12_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_12_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_13_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_13_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_13_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_13_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_14_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_14_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_14_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_14_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_15_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_15_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_15_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_15_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_16_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_16_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_16_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_16_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_17_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_17_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_17_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_17_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_18_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_18_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_18_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_18_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_19_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_19_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_19_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_19_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_20_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_20_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_20_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_20_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_21_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_21_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_21_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_21_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_22_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_22_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_22_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_22_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_23_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_23_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_23_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_23_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_24_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_24_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_24_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_24_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_25_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_25_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_25_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_25_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_26_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_26_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_26_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_26_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_27_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_27_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_27_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_27_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_28_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_28_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_28_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_28_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_29_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_29_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_29_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_29_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_30_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_30_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_30_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_30_OFFSET 0

#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_31_LEN    16
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT1_31_OFFSET 12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_31_LEN    12
#define GICD_REGS_DFX_CPUIF_UPSTREAM_WRITE_PKT0_31_OFFSET 0

#define GICD_REGS_DFX_IRQRX_CNT_LEN     16
#define GICD_REGS_DFX_IRQRX_CNT_OFFSET  16
#define GICD_REGS_DFX_IRQSET_CNT_LEN    16
#define GICD_REGS_DFX_IRQSET_CNT_OFFSET 0

#define GICD_REGS_DFX_IRQACTIVE_CNT_LEN      16
#define GICD_REGS_DFX_IRQACTIVE_CNT_OFFSET   16
#define GICD_REGS_DFX_IRQDEACTIVE_CNT_LEN    16
#define GICD_REGS_DFX_IRQDEACTIVE_CNT_OFFSET 0

#define GICD_REGS_DFX_IRQCLR_CNT_LEN        16
#define GICD_REGS_DFX_IRQCLR_CNT_OFFSET     16
#define GICD_REGS_DFX_IRQRELEASE_CNT_LEN    16
#define GICD_REGS_DFX_IRQRELEASE_CNT_OFFSET 0

#define GICD_REGS_DFX_IRQMERGE_CNT_LEN    16
#define GICD_REGS_DFX_IRQMERGE_CNT_OFFSET 16

#endif // __GICD_REGS_REG_OFFSET_FIELD_H__
